|
|
Part: CD54HC367F3A
Category:
Logic
-> Buffers/Drivers
-> Non-Inverting Buffers and Drivers
Description: ti CD54HC367, High Speed CMOS Logic Non-inverting Hex Buffer/line Driver With 3-State Outputs
Company: Texas Instruments, Inc.
Datasheet: Download CD54HC367F3A datasheet File size : 312 kB
Request For quote: Find where to buy CD54HC367F3A
Datasheet text preview:
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
Data sheet acquired from Harris Semiconductor SCHS181D
November 1997 - Revised October 2003
High-Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting
Ordering Information
PART NUMBER TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC
Features
· Buffered Inputs
[ /Title (CD74 HC367 , CD74 HCT36 7, CD74 HC368 , CD74 HCT36 8) /Subject (High Speed
· High Current Bus Driver Outputs · Two Independent Three-State Enable Controls · Typical Propagation Delay tPLH, tPHL = 8ns at VCC = 5V, CL = 15pF, TA = 25oC · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
CD54HC367F3A CD54HC368F3A CD54HCT367F3A CD74HC367E CD74HC367M CD74HC367MT CD74HC367M96 CD74HC368E CD74HC368M CD74HC368MT CD74HC368M96 CD74HCT367E CD74HCT367M CD74HCT367MT CD74HCT367M96 CD74HCT368E CD74HCT368M CD74HCT368MT CD74HCT368M96
NOTE: When ordering, use the entire par t number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250.
Description
The 'HC367, 'HCT367, 'HC368, and CD74HCT368 silicon gate CMOS three-state buffers are general purpose high-speed non-inverting and inverting buffers. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits. Both circuits are capable of driving up to 15 low power Schottky inputs. The 'HC367 and 'HCT367 are non-inverting buffers, whereas the 'HC368 and CD74HCT368 are inverting buffers. These devices have two output enables, one enable (OE1) controls 4 gates and the other (OE2) controls the remaining 2 gates. The 'HCT367 and CD74HCT368 logic families are speed, function and pin compatible with the standard LS logic family.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
1
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
Pinouts
CD54HC367, CD54HCT367 (CERDIP) CD74HC367, CD74HCT367 (PDIP, SOIC) TOP VIEW
OE1 1 1A 2 1Y 3 2A 4 2Y 5 3A 6 3Y 7 GND 8 16 VCC 15 OE2 14 6A 13 6Y 12 5A 11 5Y 10 4A 9 4Y
CD54HC368 (CERDIP) CD74HC368, CD74HCT368 (PDIP, SOIC) TOP VIEW
OE1 1 1A 2 1Y 3 2A 4 2Y 5 3A 6 3Y 7 GND 8 16 VCC 15 OE2 14 6A 13 6Y 12 5A 11 5Y 10 4A 9 4Y
Functional Diagrams
HC367, HCT367
1 1
HC368, CD74HCT368
OE1
16
VCC OE2 6A
OE1
16
VCC
1A 1Y
2 3
15 14
1A 1Y
2 3
15 14
OE2 6A
2A 2Y
4
13
6Y
2A 2Y 3A
4 5 6
13
6Y
5 6
12
5A
12
5A
3A 7
11 10
5Y 4A
11 10
5Y 4A
3Y
3Y GND
7 8
GND
8
9
4Y
9
4Y
TRUTH TABLE OUTPUTS (Y) A L H X HC/HCT367 L H (Z) HC/HCT368 H L (Z)
INPUTS OE L L H
H = High Voltage Level L = Low Voltage Level X = Don't Care Z = High Impedance (OFF) State
2
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368 Logic Diagram
VCC 16 ONE OF SIX IDENTICAL CIRCUITS 2 1A 3 1Y
(NOTE 1)
GND 8
1 OE1 4 15 OE2 6 3A 10 4A 12 5A 14 6A 7 3Y 9 4Y 11 5Y 13 6Y 2A 5 2Y
NOTE: 1. Inver ter not included in HC/HCT367 FIGURE 1. LOGIC DIAGRAM FOR THE HC/HCT367 AND HC/HCT368 (OUTPUTS FOR HC/HCT367 ARE COMPLEMENTS OF THOSE SHOWN, i.e., 1Y, 2Y, ETC.)
3
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Three-State Leakage Current II ICC IOZ VCC or GND VCC or GND VIL or VIH VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -6 -7.8 0.02 0.02 0.02 6 7.8 0 VO = VCC or GND 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 8 ±0.5 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 80 ±5.0 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 160 ±10 V V V V V V V V V V V V V V V V µA µA µA SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
4
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
DC Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load Three-State Leakage Current NOTE: 3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 3) IOZ VCC to GND VCC or GND VCC -2.1 VIL or VIH VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5 5.5
-
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
VO = VCC or GND
-
-
±0.5
-
±5.0
-
±10
µA
HCT Input Loading Table
INPUT OE1 All Others UNIT LOADS 0.6 0.55
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
TEST CONDITIONS 25oC VCC (V) 2 4.5 6 CL = 15pF 5 TYP MAX -40oC TO 85oC MAX -55oC TO 125oC MAX UNITS
PARAMETER HC TYPES Propagation Delay, Data to Outputs HC/HCT367
SYMBOL
tPLH, tPHL
CL = 50pF
8
105 21 18 -
130 26 24 -
160 32 27 -
ns ns ns ns
5
Others parts begin by cd
CD-1 CD-2 CD-3 CD-4 CD-5 CD-6 CD-7 CD-8 CD-9 CD-10 CD-11 CD-12 CD-13 CD-14 CD-15 CD-16 CD-17 CD-18 CD-19 CD-20 CD-21 CD-22 CD-23 CD-24 CD-25 CD-26 CD-27 CD-28 CD-29 CD-30 CD-31 CD-32 CD-33 CD-34 CD-35 CD-36 CD-37
|
|
|
