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Part: CD54HCT14F3A
Category:
Logic
-> Gates
-> Inverters Gates
Description: ti CD54HCT14, High Speed CMOS Logic Hex Inverting Schmitt Trigger
Company: Texas Instruments, Inc.
Datasheet: Download CD54HCT14F3A datasheet File size : 251 kB
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Datasheet text preview:
CD54HC14, CD74HC14, CD54HCT14, CD74HCT14
Data sheet acquired from Harris Semiconductor SCHS129C
January 1998 - Revised September 2003
High-Speed CMOS Logic Hex Inverting Schmitt Trigger
Description
The 'HC14 and 'HCT14 each contain six inver ting Schmitt triggers in one package.
Features
· Unlimited Input Rise and Fall Times
[ /Title (CD74H C14, CD74H CT14) /Subject (High Speed CMOS Logic Hex Invert-
· Exceptionally High Noise Immunity · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC14F3A CD54HCT14F3A CD74HC14E CD74HC14M CD74HC14MT CD74HC14M96 CD74HCT14E CD74HCT14M CD74HCT14MT CD74HCT14M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC
NOTE: When ordering, use the entire par t number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250.
Pinout
CD54HC14, CD54HCT14 (CERDIP) CD74HC14, CD74HCT14 (PDIP, SOIC) TOP VIEW
1A 1 1Y 2 2A 3 2Y 4 3A 5 3Y 6 GND 7 14 VCC 13 6A 12 6Y 11 5A 10 5Y 9 4A 8 4Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
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CD54HC14, CD74HC14, CD54HCT14, CD74HCT14 Functional Diagram
1A 1 2 1Y
2A
3
4
2Y
3A
5
6
3Y
4A
9
8
4Y
5A
11
10
5Y
6A
13
12
6Y GND = 7 VCC = 14
TRUTH TABLE INPUT (A) L H H= High Level L= Low Level OUTPUT (Y) H L
Logic Diagram
nA nY
VO
VH VH = VT+ - VTVI VTV T+ VT+ VT -
VCC VI GND VCC VO GND VH
FIGURE 3. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SETUP
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CD54HC14, CD74HC14, CD54HCT, CD74HCT14
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time, tr, tf 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES Input Switch Points VT+ 2 4.5 6 VT2 4.5 6 VH 2 4.5 6 High Level Output Voltage CMOS Loads VOH VT- or VT+ -0.02 -0.02 -0.02 High Level Output Voltage TTL Loads -4 -5.2 2 4.5 6 4.5 6 0.7 1.7 2.1 0.3 0.9 1.2 0.2 0.4 0.6 1.9 4.4 5.9 3.98 5.48 1.5 3.15 4.2 1.0 2.2 3.0 1.0 1.4 1.6 0.7 1.7 2.1 0.3 0.9 1.2 0.2 0.4 0.6 1.9 4.4 5.9 3.84 5.34 1.5 3.15 4.2 1.0 2.2 3.0 1.0 1.4 1.6 0.7 1.7 2.1 0.3 0.9 1.2 0.2 0.4 0.6 1.9 4.4 5.9 3.7 5.2 1.5 3.15 4.2 1.0 2.2 3.0 1.0 1.4 1.6 V V V V V V V V V V V V V V V SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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CD54HC14, CD74HC14, CD54HCT14, CD74HCT14
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER Low Level Output Voltage CMOS Loads SYMBOL VOL VI (V) VIH or VIL IO (mA) VCC (V) 0.02 0.02 0.02 Low Level Output Voltage TTL Loads 4 5.2 Input Leakage Current Quiescent Device Current HCT TYPES Input Switch Points VT+ 4.5 5.5 VT4.5 5.5 VH 4.5 5.5 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current II VCC and GND VCC or GND VCC - 2.1 VOL VIH or VIL VOH VIH or VIL -0.02 -4 0.02 4 4.5 4.5 4.5 4.5 5.5 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.98 1.9 2.1 1.2 1.4 1.4 1.5 0.1 0.26 ±0.1 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.84 1.9 2.1 1.2 1.4 1.4 1.5 0.1 0.33 ±1 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.7 1.9 2.1 1.2 1.4 1.4 1.5 0.1 0.4 ±1 V V V V V V V V V V µA II ICC VCC or GND VCC or GND 0 2 4.5 6 4.5 6 6 6 MIN 25oC MAX 0.1 0.1 0.1 0.26 0.26 ±0.1 2 -40oC TO 85oC MIN MAX 0.1 0.1 0.1 0.33 0.33 ±1 20 -55oC TO 125oC MIN MAX 0.1 0.1 0.1 0.4 0.4 ±1 40 UNITS V V V V V V µA µA
Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE:
ICC ICC (Note 2)
0 -
5.5 4.5 to 5.5
-
2 360
-
20 450
-
40 490
µA µA
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT nA UNIT LOADS 0.6
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC.
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Switching Specifications Input tr, tf = 6ns
PARAMETER HC TYPES Propagation Delay, A to Y tPLH, tPHL CL = 50pF CL = 50pF CL = 15pF CL = 50pF Output Transition Times tTLH, tTHL CL = 50pF 2 4.5 5 6 2 4.5 6 Input Capacitance Power Dissipation Capacitance (Notes 3, 4) HCT TYPES Propagation Delay, A to Y Output Transition Times Input Capacitance Power Dissipation Capacitance (Notes 3, 4) NOTES: 3. CPD is used to determine the dynamic power consumption, per inverter. 4. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. tPLH, tPHL CL = 50pF CL = 15pF tTLH, tTHL CI CPD CL = 50pF 4.5 5 4.5 5 16 20 38 15 10 48 19 10 57 22 10 ns ns ns pF pF CI CPD 5 11 20 135 27 23 75 15 13 10 170 34 29 95 19 16 10 18 205 41 35 110 22 19 10 ns ns ns ns ns ns ns pF pF SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
Test Circuits and Waveforms
tr = 6ns INPUT 90% 50% 10% tTLH 90% 50% 10% tPHL tPLH tf = 6ns VCC INPUT GND tTHL tr = 6ns 2.7V 1.3V 0.3V tTLH 90% INVERTING OUTPUT tPHL tPLH 1.3V 10% tf = 6ns 3V
GND
tTHL
INVERTING OUTPUT
FIGURE 4. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
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