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Part: CD54HCT153F3A
Category:
Logic
-> Encoders/Multiplexers
-> Multiplexers
Description: ti CD54HCT153, High Speed CMOS Logic Dual 4-Input Multiplexers
Company: Texas Instruments, Inc.
Datasheet: Download CD54HCT153F3A datasheet File size : 251 kB
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Datasheet text preview:
CD54HC153, CD74HC153, CD54HCT153, CD74HCT153
Data sheet acquired from Harris Semiconductor SCHS151C
September 1997 - Revised October 2003
High-Speed CMOS Logic Dual 4- to 1-Line Selector/Multiplexer
Description
The 'HC153 and 'HCT153 are dual 4- to 1-line selector/multiplexers that select one of four sources for each section by the common select inputs, S0 and S1. When the enable inputs (1E, 2E) are HIGH, the outputs are in the LOW state.
Features
· Common Select Inputs
[ /Title (CD74H C153, CD74H CT153) /Subject (High Speed CMOS Logic Dual 4Input
· Separate Enable Inputs · Buffered inputs and Outputs · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC153F3A CD54HCT153F3A CD74HC153E CD74HC153M CD74HC153MT CD74HC153M96 CD74HCT153E CD74HCT153M CD74HCT153MT CD74HCT153M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC
NOTE: When ordering, use the entire par t number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250.
Pinout
CD54HC153, CD54HCT153 (CERDIP) CD74HC153, CD74HCT153 (PDIP, SOIC) TOP VIEW
1E 1 S1 2 1I3 3 1I2 4 1I1 5 1I0 6 1Y 7 GND 8 16 VCC 15 2E 14 S0 13 2I3 12 2I2 11 2I1 10 2I0 9 2Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
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CD54HC153, CD74HC153, CD54HCT153, CD74HCT153 Functional Diagram
1 1E 6 1I0 5 1I1 4 1I2 3 1I3 S0 S1 2I0 2I1 2I2 2I3 2E 14 2 10 11 9 12 13 15 GND = 8 VCC = 16 SEL/MUX 2Y SEL/MUX 7 1Y
TRUTH TABLE SELECT INPUTS S1 X L L L L H H H H S0 X L L H H L L H H I0 X L H X X X X X X DATA INPUTS I1 X X X L H X X X X I2 X X X X X L H X X I3 X X X X X X X L H ENABLE E H L L L L L L L L OUTPUT Y L L H L H L H L H
H = High Voltage Level, L = Low Voltage Level, X = Don't Care NOTE: Select inputs S1 and S0 are common to both sections.
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CD54HC153, CD74HC153, CD54HCT153, CD74HCT153
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 160 V V V V V V V V V V V V V V V V V V µA µA SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
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CD54HC153, CD74HC153, CD54HCT153, CD74HCT153
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II ICC ICC (Note 2) VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
-
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT Data Enable Select UNIT LOADS 0.45 0.6 1.35
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g. 360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
TEST SYMBOL CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
PARAMETER HC TYPES Propagation Delay (Figure 1) S to Y
tPLH, tPHL
CL = 50pF
2 4.5
-
13 -
160 32 27
-
200 40 34
-
240 48 41
ns ns ns ns
CL =15pF CL = 50pF
5 6
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CD54HC153, CD74HC153, CD54HCT153, CD74HCT153
Switching Specifications Input tr, tf = 6ns (Continued)
TEST SYMBOL CONDITIONS tPLH, tPHL CL = 50pF VCC (V) 2 4.5 CL =15pF CL = 50pF E to Y tPLH, tPHL CL = 50pF 5 6 2 4.5 CL =15pF CL = 50pF Output Transition Time (Figure 1) tTLH, tTHL CL = 50pF 5 6 2 4.5 6 Input Capacitance Power Dissipation Capacitance (Notes 3, 4) HCT TYPES Propagation Delay (Figure 2) S to Y tPLH, tPHL CL = 50pF CL =15pF I to Y tPLH, tPHL tPLH, tPHL tPLH, tPHL CL = 50pF CL =15pF CL = 50pF CL =15pF CL = 50pF CL =15pF 4.5 5 4.5 5 4.5 5 4.5 5 4.5 5 14 11 45 14 9 34 24 34 27 15 10 19 10 30 43 34 43 51 36 51 41 22 10 ns ns ns ns ns ns ns ns ns pF pF CIN CPD 5 25oC MIN 9 45 TYP 12 MAX 145 29 25 120 24 20 75 15 13 10 -40oC TO 85oC MIN MAX 180 36 31 150 30 26 95 19 16 10 -55oC TO 125oC MIN MAX 220 44 38 180 36 31 110 22 19 10 UNITS ns ns ns ns ns ns ns ns ns ns ns pF pF
PARAMETER I to Y
I to Y
E to Y
Output Transition Time Input Capacitance Power Dissipation Capacitance (Notes 3, 4)
tTLH, tTHL CL = 50pF CIN CPD -
NOTES: 3. CPD is used to determine the dynamic power consumption, per multiplexer. 4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuit and Waveform
tr = 6ns E I OR S tf = 6ns 90% VS 10% VS OUTPUT Y tPLH tPHL
FIGURE 1. PROPAGATION DELAY TIMES
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