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Part: CD54HCT154
Category:
Logic
-> Decoder/Demultiplexers
-> CMOS/BiCMOS->HC/HCT Family
Description: High Speed CMOS Logic 4-to-16 Line Decoder/demultiplexer
Company: Texas Instruments, Inc.
Datasheet: Download CD54HCT154 datasheet File size : 251 kB
Request For quote: Find where to buy CD54HCT154
Datasheet text preview:
CD54/74HC154, CD54/74HCT154
Data sheet acquired from Harris Semiconductor SCHS152B
September 1997 - Revised October 2002
High Speed CMOS Logic 4-to-16 Line Decoder/Demultiplexer
four input lines, A0 to A3, to select the output lines Y0 to Y15, and using one enable as the data input while holding the other enable low.
Features [ /Title (CD74 HC154 , CD74 HCT15 4) /Subject (High Speed CMOS Logic 4-to-16 Line Decod er/Dem
· Two Enable Inputs to Facilitate Demultiplexing and Cascading Functions · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times
Ordering Information
PART NUMBER CD54HC154F3A CD74HC154E TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 24 Ld CERDIP 24 Ld PDIP 24 Ld PDIP 24 Ld SOIC 24 Ld SOIC 24 Ld CERDIP 24 Ld PDIP 24 Ld PDIP 24 Ld SOIC
· Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
CD74HC154EN CD74HC154M CD74HC154M96 CD54HCT154F3A CD74HCT154E CD74HCT154EN CD74HCT154M NOTES:
Description
The 'HC154 and 'HCT154 are 4-to-16 line decoders/demultiplexers with two enable inputs, E1 and E2. A High on either enable input forces the output into the High state. The demultiplexing function is performed by using the
1. When ordering, use the entire par t number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer or die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information.
Pinout
CD54HC154, CD54HCT154 (CERDIP) CD74HC154, CD74HCT154 (PDIP, SOIC) TOP VIEW
Y0 1 Y1 2 Y2 3 Y3 4 Y4 5 Y5 6 Y6 7 Y7 8 Y8 9 Y9 10 Y10 11 GND 12 24 VCC 23 A0 22 A1 21 A2 20 A3 19 E2 18 E1 17 Y15 16 Y14 15 Y13 14 Y12 13 Y11
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2002, Texas Instruments Incorporated
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CD54/74HC154, CD54/74HCT154 Functional Diagram
1 2 3 4 5 6 7 A0 23 A1 22 A2 A3 21 20 8 9 10 11 13 14 15 E1 E2 18 19 16 17 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 GND = 12 VCC = 24
TRUTH TABLE INPUTS E1 L L L L L L L L L L L L L L L L L H H E2 L L L L L L L L L L L L L L L L H L H A3 L L L L L L L L H H H H H H H H X X X A2 L L L L H H H H L L L L H H H H X X X A1 L L H H L L H H L L H H L L H H X X X A0 L H L H L H L H L H L H L H L H X X X Y0 L H H H H H H H H H H H H H H H H H H Y1 H L H H H H H H H H H H H H H H H H H Y2 H H L H H H H H H H H H H H H H H H H Y3 H H H L H H H H H H H H H H H H H H H Y4 H H H H L H H H H H H H H H H H H H H Y5 H H H H H L H H H H H H H H H H H H H Y6 H H H H H H L H H H H H H H H H H H H OUTPUTS Y7 H H H H H H H L H H H H H H H H H H H Y8 H H H H H H H H L H H H H H H H H H H Y9 H H H H H H H H H L H H H H H H H H H Y10 H H H H H H H H H H L H H H H H H H H Y11 H H H H H H H H H H H L H H H H H H H Y12 H H H H H H H H H H H H L H H H H H H Y13 H H H H H H H H H H H H H L H H H H H Y14 H H H H H H H H H H H H H H L H H H H Y15 H H H H H H H H H H H H H H H L H H H
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don't Care
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CD54/74HC154, CD54/74HCT154
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical) JA (oC/W) E Package (.300) (Note 3) . . . . . . . . . . . . . . . . . . . . 67 EN Package (.600) (Note 3) . . . . . . . . . . . . . . . . . . 67 M Package (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . 46 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. The package thermal impedance is calculated in accordance with JESD 51-3. 4. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 160 V V V V V V V V V V V V V V V V V V µA µA SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
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CD54/74HC154, CD54/74HCT154
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II ICC ICC VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT A0 - A3 E1, E2 UNIT LOADS 1.4 1.3
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
TEST CONDITIONS 25oC VCC (V) MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
PARAMETER HC TYPES Propagation Delay (Figure 1) Address to Output
SYMBOL
tPLH, tPHL CL = 50pF
2 4.5
-
14 14 -
175 35 30 175 35 30
-
220 44 37 220 44 37
-
265 53 45 265 53 45
ns ns ns ns ns ns ns ns
CL =15pF CL = 50pF E1 to Output tPLH, tPHL CL = 50pF
5 6 2 4.5
CL =15pF CL = 50pF
5 6
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CD54/74HC154, CD54/74HCT154
Switching Specifications Input tr, tf = 6ns (Continued)
TEST CONDITIONS 25oC VCC (V) 2 4.5 CL =15pF CL = 50pF Output Transition Time (Figure 1) tTLH, tTHL CL = 50pF 5 6 2 4.5 6 Input Capacitance Power Dissipation Capacitance (Notes 5, 6) HCT TYPES Propagation Delay (Figure 2) Address to Output tPLH, tPHL CL = 50pF CL =15pF E1 to Output tPLH, tPHL CL = 50pF CL =15pF E2 to Output tPLH, tPHL CL = 50pF CL =15pF Output Transition Time Input Capacitance Power Dissipation Capacitance (Notes 5, 6) NOTES: 5. CPD is used to determine the dynamic power consumption, per gate. 6. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. tTLH, tTHL CL = 50pF CIN CPD 4.5 5 4.5 5 4.5 5 4.5 5 14 84 14 14 35 34 34 15 10 43 43 19 10 44 53 51 51 22 10 ns ns ns ns ns ns ns pF pF CIN CPD 5 MIN TYP 14 88 MAX 175 35 30 75 15 13 10 -40oC TO 85oC MIN MAX 220 44 37 95 19 16 10 -55oC TO 125oC MIN MAX 265 53 45 110 22 19 10 UNITS ns ns ns ns ns ns ns pF pF
PARAMETER E2 to Output
SYMBOL
tPLH, tPHL CL = 50pF
Test Circuits and Waveforms
tr = 6ns INPUT 90% 50% 10%
tf = 6ns VCC
tr = 6ns INPUT GND 2.7V 1.3V 0.3V
tf = 6ns 3V
GND tTLH 90%
tTHL
tTLH 90% 50% 10% tPHL tPLH
tTHL
INVERTING OUTPUT
INVERTING OUTPUT tPHL tPLH
1.3V 10%
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
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