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Part: CD54HCT157
Category:
Logic
-> Multiplexers/Demultiplexers
-> Multiplexers->CMOS/BiCMOS->HC/HCT Family
Description: High Speed CMOS Logic Quad 2-input Multiplexers
Company: Texas Instruments, Inc.
Datasheet: Download CD54HCT157 datasheet File size : 251 kB
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Datasheet text preview:
CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158
Data sheet acquired from Harris Semiconductor SCHS153A
September 1997 - Revised May 2000
High Speed CMOS Logic Quad 2-Input Multiplexers
Description
The 'HC157, 'HCT157, 'HC158, and 'HCT158 are quad 2input multiplexers which select four bits of data from two sources under the control of a common Select input (S). The Enable input (E) is active Low. When (E) is High, all of the outputs in the 158, the inver ting type, (1Y-4Y) are forced High and in the 157, the non-inver ting type, all of the outputs (1Y-4Y) are forced Low, regardless of all other input conditions. Moving data from two groups of registers to four common output busses is a common use of these devices. The state of the Select input determines the par ticular register from which the data comes. They can also be used as function generators.
Features
· Common Select Inputs
[ /Title (CD74H C157, CD74H CT157, CD74H C158, CD74H CT158) /Subject High peed
· Separate Enable Inputs · Buffered inputs and Outputs · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC157F CD54HC157F3A CD74HC157E CD74HC157M CD54HCT157F3A TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld CERDIP 16 Ld PDIP
Pinout
CD54HC157, CD54HCT157, CD54HC158, CD54HCT158 (CERDIP) CD74HC157, CD74HCT157, CD74HC158, CD74HCT158 (PDIP, SOIC) TOP VIEW
S1 1I0 2 1I1 3 1Y 4 2I0 5 2I1 6 2Y 7 GND 8 16 VCC 15 E 14 4I0 13 4I1 12 4Y 11 3I0 10 3I1 9 3Y
CD74HCT157E CD74HCT157M CD54HC158F3A CD74HC158E CD74HC158M CD54HCT158F3A CD74HCT158E NOTES:
1. When ordering, use the entire par t number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer or die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2000, Texas Instruments Incorporated
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CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158 Functional Diagram
HC/HCT HC/HCT 157 158 1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1 S E 2 3 5 6 11 10 14 13 1 15 4 1Y 1Y
7 2Y 2Y
9 3Y 3Y
12 4Y 4Y
TRUTH TABLE OUTPUT ENABLE E H L L L L SELECT INPUT S X L L H H DATA INPUTS I0 X L H X X I1 X X X L H 157 Y L L H L H 158 Y H H L H L
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don't Care
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CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 3) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 160 V V V V V V V V V V V V V V V V V V µA µA SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
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CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II ICC ICC VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
UNIT LOADS INPUT I (All) E S HCT157 0.95 0.6 3 HCT158 0.4 0.6 2.8
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
PARAMETER HC/HCT157 TYPES Propagation Delay (Figure 1) tPLH, tPHL CL = 50pF Data to Output HC157 HCT157 CL = 50pF 6 CL =15pF 2 4.5 5 10 12 125 25 21 155 31 26 190 38 32 ns ns ns ns ns SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER Enable to Output SYMBOL TEST CONDITIONS VCC (V) 2 4.5 HC157 HCT157 CL = 50pF Select to Output tPLH, tPHL CL = 50pF 6 2 4.5 HC157 HCT157 CL = 50pF Power Dissipation Capacitance (Notes 4, 5) HC157 HCT157 HC/HCT158 TYPES Data to Output tPLH, tPHL CL = 50pF 2 4.5 HC158 HCT 158 CL = 50pF Enable to Output tPLH, tPHL CL = 50pF 6 2 4.5 HC158 HCT 158 CL = 50pF Select to Output tPLH, tPHL CL = 50pF 6 2 4.5 HC158 HCT 158 CL = 50pF Output Transition Time tTLH, tTHL CL = 50pF 6 2 4.5 6 Power Dissipation Capacitance (Notes 4, 5) HC158 HCT 158 Input Capacitance NOTES: 4. CPD is used to determine the dynamic power consumption, per multiplexer. 5. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. CIN CL = 50pF CPD 5 35 35 10 10 10 pF pF pF CL =15pF 5 CL =15pF 5 CL =15pF 5 11 13 13 15 12 14 140 28 24 160 32 27 150 30 26 75 15 13 175 35 30 200 40 34 190 38 33 95 19 16 210 42 36 240 48 41 225 45 38 110 22 19 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CPD 6 5 62 70 pF pF CL =15pF 5 CL =15pF 5 25oC MIN TYP 11 12 12 15 MAX 135 27 23 145 29 25 -40oC TO 85oC MIN MAX 170 34 29 180 36 31 -55oC TO 125oC MIN MAX 205 41 35 220 44 38 UNITS ns ns ns ns ns ns ns ns ns ns
tPLH, tPHL CL = 50pF
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