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Part: CD54HCT165F3A
Category:
Logic
-> Registers
Description: ti CD54HCT165, High Speed CMOS Logic 8-Bit Parallel-in/serial-out Shift Register
Company: Texas Instruments, Inc.
Datasheet: Download CD54HCT165F3A datasheet File size : 251 kB
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Datasheet text preview:
CD54HC165, CD74HC165, CD54HCT165, CD74HCT165
Data sheet acquired from Harris Semiconductor SCHS156C
February 1998 - Revised October 2003
High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register
Description
The 'HC165 and 'HCT165 are 8-bit parallel or serial-in shift registers with complementar y serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When the PL is HIGH, data enters the register serially at the DS input and shifts one place to the right (Q0Q1Q2, etc.) with each positive-going clock transition. This feature allows parallelto-serial conver ter expansion by typing the Q7 output to the DS input of the succeeding device. For predictable operation the LOW-to-HIGH transition of CE should only take place while CP is HIGH. Also, CP an d CE should be LOW before the LOW-to-HIGH transition of PL to prevent shifting the data when PL goes HIGH.
Features
· Buffered Inputs
[ /Title (CD74H C165, CD74H CT165) /Subject (High Speed CMOS Logic 8Bit Parallel-
· Asynchronous Parallel Load · Complementary Outputs · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC165F3A CD54HCT165F3A CD74HC165E TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC
Pinout
CD54HC165, CD54HCT165 (CERDIP) CD74HC165, CD74HCT165 (PDIP, SOIC) TOP VIEW
PL 1 CP 2 D4 3 D5 4 D6 5 D7 6 Q7 7 GND 8 16 VCC 15 CE 14 D3 13 D2 12 D1 11 D0 10 DS 9 Q7
CD74HC165M CD74HC165MT CD54HC165M96 CD74HCT165E CD74HCT165M CD74HCT165MT CD54HCT165M96
NOTE: When ordering, use the entire par t number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
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CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 Functional Diagram
D0 D1 D2 PARALLEL DATA INPUTS D3 D4 D5 D6 D7 DS PL CE CP 11 12 13 14 3 4 5 6 10 1 15 2 GND = 8 VCC = 16 7 Q7 9 Q7 SERIAL OUTPUTS
TRUTH TABLE INPUTS OPERATING MODE Parallel Load PL L L Serial Shift H H Hold Do Nothing H h l L X qn H CE X X L L H CP X X X DS X X l h X D0 - D7 L H X X X Qn REGISTER Q0 L H L H q0 Q 1 - Q6 L-L H-H q0 - q5 q0 - q5 q1 - q6 OUTPUTS Q7 L H q6 q6 q7 Q7 H L q6 q6 q7
=High Voltage Level = High Voltage Level One Set-up Time Prior To The Low-to-high Clock Transition = Low Voltage Level One Set-up Time Prior To The Low-to-high Clock Transition = Low Voltage Level = Don't Care = Transition from Low to High Level = Lower Case Letters Indicate The State Of the Reference Output Clock Transition
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CD54HC165, CD74HC165, CD54HCT165, CD74HCT165
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current per Output, IO For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 V V V V V V V V V V V V V V V V µA SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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CD54HC165, CD74HC165, CD54HCT165, CD74HCT165
DC Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Quiescent Device Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 2) VCC to GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL ICC VI (V) VCC or GND IO (mA) VCC (V) 0 6 MIN 25oC TYP MAX 8 -40oC TO 85oC MIN MAX 80 -55oC TO 125oC MIN MAX 160 UNITS µA
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
-
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
HCT Input Loading Table
INPUT DS, D0 to D7 CP, PL UNIT LOADS 0.35 0.65
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC.
Prerequisite For Switching Specifications
25oC PARAMETER HC TYPES CP Pulse Width tWL, tWH 2 4.5 6 80 16 14 100 20 17 120 24 20 ns ns ns SYMBOL VCC (V) MIN MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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CD54HC165, CD74HC165, CD54HCT165, CD74HCT165
Prerequisite For Switching Specifications
(Continued) 25oC PARAMETER PL Pulse Width SYMBOL tWL VCC (V) 2 4.5 6 Set-up Time DS to CP tSU 2 4.5 6 CE to CP tSU(L) 2 4.5 6 D0-D7 to PL tSU 2 4.5 6 Hold Time DS to CP or CE tH 2 4.5 6 CE to CP tH 2 4.5 6 Recovery Time PL to CP tREC 2 4.5 6 Maximum Clock Pulse Frequency fMAX 2 4.5 6 HCT TYPES CP Pulse Width PL Pulse Width Set-up Time DS to CP CE to CP D0-D7 to PL Hold Time DS to CP or CE CE to CP Recovery Time PL to CP Maximum Clock Pulse Frequency tWL, tWH tWL tSU tSU(L) tSU tH tS, tH tREC fMAX 4.5 4.5 4.5 4.5 6 4.5 4.5 4.5 4.5 18 20 20 20 20 7 0 20 27 23 25 25 25 25 9 0 25 22 27 30 30 30 30 11 0 30 18 ns ns ns ns ns ns ns ns MHz MIN 80 16 14 80 16 14 80 16 14 80 16 14 35 7 6 0 0 0 100 20 17 6 30 35 MAX -40oC TO 85oC MIN 100 20 17 100 20 17 100 20 17 100 20 17 45 9 8 0 0 0 125 25 21 5 24 28 MAX -55oC TO 125oC MIN 120 24 20 120 24 20 120 24 20 120 24 20 55 11 9 0 0 0 150 30 26 4 20 24 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz
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