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Part: CD54HCT166
Category:
Logic
-> Registers
-> CMOS/BiCMOS->HC/HCT Family
Description: High Speed CMOS Logic Bit Parallel-in/serial-out Shift Register
Company: Texas Instruments, Inc.
Datasheet: Download CD54HCT166 datasheet File size : 251 kB
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Datasheet text preview:
CD54/74HC166, CD54/74HCT166
Data sheet acquired from Harris Semiconductor SCHS157A
February 1998 - Revised May 2000
High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register
Ordering Information
PART NUMBER CD54HC166F3A CD74HC166E CD74HC166M CD54HCT166F3A CD74HCT166E CD74HCT166M NOTES: 1. When ordering, use the entire par t number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC
Features
· Buffered Inputs
[ /Title (CD74 HC166 , CD74 HCT16 6) /Subject High peed MOS ogic -Bit araleln/Seri
· Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Pinout
CD54HC166, CD54HCT166 (CERDIP) CD74HC166, CD74HCT166 (PDIP, SOIC) TOP VIEW
DS 1 D0 2 D1 3 D2 4 D3 5 CE 6 CP 7 GND 8 16 VCC 15 PE 14 D7 13 Q7 12 D6 11 D5 10 D4 9 MR
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2000, Texas Instruments Incorporated
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CD54/74HC166, CD54/74HCT166 Description
The 'HC166 and 'HCT166 8-bit shift register is fabricated with silicon gate CMOS technology. It possesses the low power consumption of standard CMOS integrated circuits, and can operate at speeds comparable to the equivalent low power Schottky device. The 'HCT166 is functionally as well as pin compatible with the standard 'LS166. The 166 is an 8-bit shift register that has fully synchronous serial or parallel data entry selected by an active LOW Parallel Enable (PE) input. When the PE is LOW one setup time before the LOW-to-HIGH clock transition, parallel data is entered into the register. When PE is HIGH, data is entered into the internal bit position Q0 from Serial Data Input (DS), and the remaining bits are shifted one place to the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. For expansion of the register in parallel to serial converters, the Q7 output is connected to the DS input of the succeeding stage. The clock input is a gated OR structure which allows one input to be used as an active LOW Clock Enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of CE input should only take place while the CP is HIGH for predictable operation. A LOW on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all bit positions to a LOW state.
Functional Diagram
D0 D1 D2 D3 D4 D5 D6 D7 PE PARALLEL ENABLE CIRCUIT D0 DS 8 - REGISTERS Q7 CP CE MR D7
TRUTH TABLE INPUTS PARALLEL MASTER RESET L H H H H H PARALLEL ENABLE X X L H H X CLOCK ENABLE X L L L L H CLOCK X L SERIAL X X X H L X D0 D7 X X a...h X X X Q0 L Q00 a H L Q00 INTERNAL Q STATES Q1 L Q10 b Q0n Q0n Q10 OUTPUT Q7 L Q0 h Q6n Q6n Q70
NOTES: H = High Voltage Level L = Low Voltage Level X = Don't Care = Transition from Low to High Level a...h = The level of steady-state input at inputs D0 thru D7, respectively. Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady-state input conditions were established. Q0n, Q6n = The level of Q0 or Q6, respectively, before the most recent transition of the clock.
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CD54/74HC166, CD54/74HCT166
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 3) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 V V V V V V V V V V V V V V V V µA SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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CD54/74HC166, CD54/74HCT166
DC Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Quiescent Device Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load (Note 4) NOTE: 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC VCC to GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL ICC VI (V) VCC or GND IO (mA) VCC (V) 0 6 MIN 25oC TYP MAX 8 -40oC TO 85oC MIN MAX 80 -55oC TO 125oC MIN MAX 160 UNITS µA
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
-
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
HCT Input Loading Table
INPUT DS, D0-D7 PE CP, CE MR UNIT LOADS 0.2 0.35 0.5 0.2
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC.
Prerequisite For Switching Specifications
25oC PARAMETER HC TYPES Clock Frequency (Figure 1) fMAX 2 4.5 6 6 30 35 5 25 29 4 20 23 MHz MHz MHz SYMBOL VCC (V) MIN MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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CD54/74HC166, CD54/74HCT166
Prerequisite For Switching Specifications (Continued)
25oC PARAMETER MR Pulse Width (Figure 1) SYMBOL tw VCC (V) 2 4.5 6 Clock Pulse Width (Figure 1) tW 2 4.5 6 Set-up Time Data and CE to Clock (Figure 5) Hold Time Data to Clock (Figure 5) Removal Time MR to Clock (Figure 5) Set-up Time PE to CP (Figure 5) Hold Time PE to CP or CE (Figure 5) HCT TYPES Clock Frequency (Figure 2) MR Pulse Width (Figure 2) Clock Pulse Width (Figure 2) Set-up Time Data and CE to Clock (Figure 6) Hold Time Data to Clock (Figure 6) Removal Time MR to Clock (Figure 6) Set-up Time PE to CP (Figure 6) Hold Time PE to CP or CE (Figure 6) fMAX tw tw tSU tH tREM tSU tH 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 25 35 20 16 0 0 30 0 20 44 25 20 0 0 38 0 16 53 30 24 0 0 45 0 MHz ns ns ns ns ns ns ns tSU 2 4.5 6 tH 2 4.5 6 tREM 2 4.5 6 tSU 2 4.5 6 tH 2 4.5 6 MIN 100 20 17 80 16 14 80 16 14 1 1 1 0 0 0 145 29 25 0 0 0 MAX -40oC TO 85oC MIN 125 25 21 100 20 17 100 20 17 1 1 1 0 0 0 180 36 31 0 0 0 MAX -55oC TO 125oC MIN 150 30 26 120 24 20 120 24 20 1 1 1 0 0 0 220 44 38 0 0 0 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Switching Specifications Input tr, tf = 6ns
PARAMETER HC TYPES Propagation Delay, Clock to Output (Figure 3) SYMBOL tPLH, tPHL TEST CONDITIONS CL = 50pF CL = 15pF CL = 50pF 25oC VCC (V) 2 4.5 5 6 TYP 13 MAX 160 32 27 -40oC TO 85oC -55oC TO 125oC MAX 200 40 34 MAX 240 48 41 UNITS ns ns ns ns
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