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Part: CD54HCT173
Category:
Logic
-> Flip-Flops
-> CMOS/BiCMOS->HC/HCT Family
Description: High Speed CMOS Logic Quad D-type Flip-flop, Three-state
Company: Texas Instruments, Inc.
Datasheet: Download CD54HCT173 datasheet File size : 251 kB
Request For quote: Find where to buy CD54HCT173
Datasheet text preview:
CD54/74HC173, CD54/74HCT173
Data sheet acquired from Harris Semiconductor SCHS158C
February 1998 - Revised July 2002
High Speed CMOS Logic Quad D-Type Flip-Flop, Three-State
Description
The 'HC173 and 'HCT173 high speed three-state quad Dtype flip-flops are fabricated with silicon gate CMOS technology. They possess the low power consumption of standard CMOS Integrated circuits, and can operate at speeds comparable to the equivalent low power Schottky devices. The buffered outputs can drive 15 LSTTL loads. The large output drive capability and three-state feature make these par ts ideally suited for interfacing with bus lines in bus oriented systems. The four D-type flip-flops operate synchronously from a common clock. The outputs are in the three-state mode when either of the two output disable pins are at the logic "1" level. The input ENABLES allow the flip-flops to remain in their present states without having to disrupt the clock If either of the 2 input ENABLES are taken to a logic "1" level, the Q outputs are fed back to the inputs, forcing the flip-flops to remain in the same state. Reset is enabled by taking the MASTER RESET (MR) input to a logic "1" level. The data outputs change state on the positive going edge of the clock. The 'HCT173 logic family is functionally, as well as pin compatible with the standard LS logic family.
Features
· Three-State Buffered Outputs
[ /Title (CD74H C173, CD74H CT173) /Subject (High Speed CMOS Logic Quad DType
· Gated Input and Output Enables · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Pinout
CD54HC173, CD54HCT173 (CERDIP) CD74HC173 (PDIP, SOIC, SOP, TSSOP) CD74HCT173 (PDIP, SOIC) TOP VIEW
OE 1 OE2 2 Q0 3 Q1 4 Q2 5 Q3 6 CP 7 GND 8 16 VCC 15 MR 14 D0 13 D1 12 D2 11 D3 10 E2 9 E1
Ordering Information
PART NUMBER CD54HC173F CD54HC173F3A CD54HCT173F3A CD74HC173E CD74HC173M CD74HC173M96 CD74HC173NSR CD74HC173PWR CD74HCT173E CD74HCT173M CD74HCT173M96 NOTES: 1. When ordering, use the entire par t number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOP 16 Ld TSSOP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2002, Texas Instruments Incorporated
1
CD54/74HC173, CD54/74HCT173 Functional Diagram
E1 E2 10 D0 D1 D2 11 D3 7 CP MR OE1 OE2 15 1 2 6 Q3 14 13 4 12 5 Q2 Q1 9 3 Q0
TRUTH TABLE INPUTS DATA ENABLE MR H L L L L L CP X L E1 X X H X L L E2 X X X H L L DATA D X X X X L H OUTPUT Qn L Q0 Q0 Q0 L H
NOTE: When either OE1 or OE2 (or both) is (are) high the output is disabled to the high-impedance state, however, sequential operation of the flip-flops is not affected. H = High Voltage Level L = Low Voltage Level X = Irrelevant = Transition from Low to High Level Q0 = Level Before the Indicated Steady-State Input Conditions Were Established
2
CD54/74HC173, CD54/74HCT173 Logic Diagram
9 E1
10 E2 D 14 D0 7 CP CP R 15 MR 1 OE1 Q N Q V CC P 3 Q0
2 OE2
13 D1 12 D2 11 D3 3 CIRCUITS IDENTICAL TO ABOVE CIRCUIT IN DASHED ENCLOSURE
4 5 6 Q3 Q1 Q2
3
CD54/74HC173, CD54/74HCT173
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA
Thermal Information
Package Thermal Impedance, JA (see Note 3): PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W SOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 -0.02 -0.02 High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL -6 -7.8 0.02 0.02 0.02 Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND 6 7.8 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 160 V V V V V V V V V V V V V V V V µA µA SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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CD54/74HC173, CD54/74HCT173
DC Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Three-State Leakage Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load (Note 4) Three-State Leakage Current NOTE: 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC VCC to GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL IOZ VI (V) VIL or VIH IO (mA) VCC (V) 6 MIN 25oC TYP MAX ±0.5 -40oC TO 85oC MIN MAX ±0.5 -55oC TO 125oC MIN MAX ±10 UNITS µA
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
6
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
-
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
IOZ
VIL or VIH
-
5.5
-
-
±0.5
-
±5.0
-
±10
µA
HCT Input Loading Table
INPUT D0-D3 E1 and E2 CP MR OE1 and OE2 UNIT LOADS 0.15 0.15 0.25 0.2 0.5
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC.
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