|
|
Part: CD54HCT174F
Category:
Logic
-> Flip-Flops
-> D-Type Flip-Flops
Description: ti CD54HCT174, High Speed CMOS Logic Hex D-type Flip-flops With Reset
Company: Texas Instruments, Inc.
Datasheet: Download CD54HCT174F datasheet File size : 251 kB
Request For quote: Find where to buy CD54HCT174F
Datasheet text preview:
CD54HC174, CD74HC174, CD54HCT174, CD74HCT174
Data sheet acquired from Harris Semiconductor SCHS159C
August 1997 - Revised October 2003
High-Speed CMOS Logic Hex D-Type Flip-Flop with Reset
times is transferred to the Q output on the low to high transition of the CLOCK input. The MR input, when low, sets all outputs to a low state. Each output can drive ten low power Schottky TTL equivalent loads. The 'HCT174 is functional as well as, pin compatible to the 'LS174.
Features
· Buffered Positive Edge Triggered Clock
[ /Title (CD74 HC174 , CD74 HCT17 4) /Subject (High Speed CMOS Logic Hex DType FlipFlop
· Asynchronous Common Reset · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC174F3A CD54HCT174F3A CD74HC174E CD74HC174M CD74HC174MT CD74HC174M96 CD74HCT174E CD74HCT174M TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC
Description
The 'HC174 and 'HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flipflops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six masterslave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold
CD74HCT174MT CD74HCT174M96
NOTE: When ordering, use the entire par t number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250.
Pinout
CD54HC174, CD54HCT174 (CERDIP) CD74HC174, CD74HCT174 (PDIP, SOIC) TOP VIEW
MR 1 Q0 2 D0 3 D1 4 Q1 5 D2 6 Q2 7 GND 8 16 VCC 15 Q5 14 D5 13 D4 12 Q4 11 D3 10 Q3 9 CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
1
CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 Functional Diagram
CP D0 CP D R
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5 MR
Q5
TRUTH TABLE INPUTS RESET (MR) L H H H CLOCK CP X L DATA Dn X H L X OUTPUT Qn L H L Q0
H = High Voltage Level, L = Low Voltage Level, X = Irrelevant, = Transition from Low to High Level, Q0 = Level Before the Indicated Steady-State Input Conditions Were Established
Logic Diagram
CL 3 (4, 6, 11, 13, 14) Dn D p n CL CL p n CL R 1 MR 9 CP CP
CL p n CL CL p n CL CL CL
ONE OF SIX F/F
Q 2 (5, 7, 10, 12, 15) Qn 8 16
TO OTHER FIVE F/F VCC TO OTHER FIVE F/F
2
CD54HC174, CD74HC174, CD54HCT174, CD74HCT174
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 160 V V V V V V V V V V V V V V V V µA µA SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO +85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
3
CD54HC174, CD74HC174, CD54HCT174, CD74HCT174
DC Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 2) VCC to GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO +85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
-
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
HCT Input Loading Table
INPUT CP MR D UNIT LOADS 0.80 0.55 0.15
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC.
Prerequisite For Switching Function
PARAMETER HC TYPES Clock Pulse Width tw 2 4.5 6 MR Pulse Width tw 2 4.5 6 80 16 14 80 16 14 100 20 17 100 20 17 120 24 20 120 24 20 ns ns ns ns ns ns SYMBOL TEST CONDITIONS VCC (V) 25oC MIN MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
4
CD54HC174, CD74HC174, CD54HCT174, CD74HCT174
Prerequisite For Switching Function
PARAMETER Setup Time, Data to Clock SYMBOL tSU (Continued) 25oC MIN 60 12 10 5 5 5 5 5 5 6 30 35 MAX -40oC TO 85oC -55oC TO 125oC MIN 75 15 13 5 5 5 5 5 5 5 24 28 MAX MIN 90 18 15 5 5 5 5 5 5 4 20 24 MAX UNITS ns ns ns ns ns ns ns ns ns MHz MHz MHz
TEST CONDITIONS VCC (V) 2 4.5 6
Hold Time, Data to Clock
tH
-
2 4.5 6
Removal Time, MR to Clock
tREM
-
2 4.5 6
Clock Frequency
fMAX
-
2 4.5 6
HCT TYPES Clock Pulse Width MR Pulse Width Setup Time, Data to Clock Hold Time, Data to Clock Removal Time, MR to Clock Clock Frequency tw tw tSU tH tREM fMAX 4.5 6 4.5 6 4.5 6 20 25 16 5 12 25 25 31 20 5 15 20 30 38 24 5 18 17 ns ns ns ns ns MHz
Switching Specifications Input tr, tf = 6ns
TEST CONDITIONS 25oC VCC (V) TYP MAX -40oC TO 85oC -55oC TO 125oC MAX MAX UNITS
PARAMETER HC TYPES Propagation Delay, Clock to Q
SYMBOL
tPLH, tPHL
CL = 50pF
2 4.5 6
13 12 38
165 33 28 150 30 26 75 15 13 10 -
205 41 35 190 38 33 95 19 16 10 -
250 50 43 225 45 38 110 22 19 10 -
ns ns ns ns ns ns ns ns ns ns ns pF pF
CL = 15pF Propagation Delay, MR to Q tPLH, tPHL CL = 50pF
5 2 4.5 6
CL = 15pF Output Transition Times tTLH, tTHL CL = 50pF
5 2 4.5 6
Input Capacitance Power Dissipation Capacitance (Notes 3, 4)
CIN CPD
-
5
5
Others parts begin by cd
CD-1 CD-2 CD-3 CD-4 CD-5 CD-6 CD-7 CD-8 CD-9 CD-10 CD-11 CD-12 CD-13 CD-14 CD-15 CD-16 CD-17 CD-18 CD-19 CD-20 CD-21 CD-22 CD-23 CD-24 CD-25 CD-26 CD-27 CD-28 CD-29 CD-30 CD-31 CD-32 CD-33 CD-34 CD-35 CD-36 CD-37
|
|
|
