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Part: CD54HCT175F3A
Category:
Logic
-> Flip-Flops
-> D-Type Flip-Flops
Description: ti CD54HCT175, High Speed CMOS Logic Quad D-type Flip-flops With Reset
Company: Texas Instruments, Inc.
Datasheet: Download CD54HCT175F3A datasheet File size : 251 kB
Request For quote: Find where to buy CD54HCT175F3A
Datasheet text preview:
CD54HC175, CD74HC175, CD54HCT175, CD74HCT175
Data sheet acquired from Harris Semiconductor SCHS160C
August 1997 - Revised October 2003
High-Speed CMOS Logic Quad D-Type Flip-Flop with Reset
advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices. Information at the D input is transferred to the Q, Q outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four Q outputs to a logic 1.
Features [ /Title (CD74 HC175 , CD74 HCT17 5) /Subject (High Speed CMOS Logic Quad DType Flip· Common Clock and Asynchronous Reset on Four D-Type Flip-Flops · Positive Edge Pulse Triggering · Complementary Outputs · Buffered Inputs · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC175F3A CD54HCT175F3A CD74HC175E CD74HC175M CD74HC175MT CD74HC175M96 CD74HCT175E CD74HCT175M CD74HCT175MT CD74HCT175M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC
Description
The 'HC175 and 'HCT175 are high speed Quad D-type FlipFlops with individual D-inputs and Q, Q complementar y outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption
NOTE: When ordering, use the entire par t number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250.
Pinout
CD54HC175, CD54HCT175 (CERDIP) CD74HC175, CD74HCT175 (PDIP, SOIC) TOP VIEW
MR 1 Q0 2 Q0 3 D0 4 D1 5 Q1 6 Q1 7 GND 8 16 VCC 15 Q3 14 Q3 13 D3 12 D2 11 Q2 10 Q2 9 CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
1
CD54HC175, CD74HC175, CD54HCT175, CD74HCT175 Functional Diagram
4 D0 CP MR 5 D1 D CP R 12 D2 D CP R 13 D3 D CP R Q Q 14 Q3 Q 15 Q3 Q 11 Q2 Q 10 Q2 Q 6 Q1 D 9 CP 1 R Q Q 3 Q0 7 Q1
2 Q0
TRUTH TABLE INPUTS RESET (MR) L H H H CLOCK CP X L DATA Dn X H L X Qn L H L Q0 OUTPUTS Qn H L H Q0
H = High Voltage Level, L = Low Voltage Level, X = Don't Care, = Transition from Low to High Level, Q0 = Level Before the Indicated Steady-State Input Conditions Were Established.
Logic Diagram
CL 4 (5, 12, 13) Dn D p n CL CL p n CL R 1 MR 9 CP TO OTHER THREE F/F GND VCC TO OTHER THREE F/F 8 16 CP CL CL p n CL CL p n CL CL 2( 7, 10, 15) Qn ONE OF FOUR F/F 3( 6, 11, 14) Qn
2
CD54HC175, CD74HC175, CD54HCT175, CD74HCT175
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 160 V V V V V V V V V V V V V V V V µA µA SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO +85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
3
CD54HC175, CD74HC175, CD54HCT175, CD74HCT175
DC Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTES: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 2) VCC to GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO +85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
-
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
HCT Input Loading Table
INPUT MR CP D UNIT LOADS 1 0.60 0.15
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC.
Prerequisite For Switching Specifications
PARAMETER HC TYPES Clock Pulse Width tw 2 4.5 6 MR Pulse Width tw 2 4.5 6 80 16 14 80 16 14 100 20 17 100 20 17 120 24 20 120 24 20 ns ns ns ns ns ns SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
4
CD54HC175, CD74HC175, CD54HCT175, CD74HCT175
Prerequisite For Switching Specifications
PARAMETER Setup Time, Data to Clock SYMBOL tSU (Continued) VCC (V) 2 4.5 6 Hold Time, Data to Clock tH 2 4.5 6 Removal Time, MR to Clock tREM 2 4.5 6 Clock Frequency fMAX 2 4.5 6 HCT TYPES Clock Pulse Width MR Pulse Width Setup Time Data to Clock Hold Time Data to Clock Removal Time MR to Clock Clock Frequency tw tw tSU tH tREM fMAX 4.5 4.5 4.5 4.5 4.5 4.5 20 20 20 5 5 25 25 25 25 5 5 20 30 30 30 5 5 16 ns ns ns ns ns MHz 25oC MIN 80 16 14 5 5 5 5 5 5 6 30 35 TYP MAX -40oC TO 85oC -55oC TO 125oC MIN 100 20 17 5 5 5 5 5 5 5 25 29 MAX MIN 120 24 20 5 5 5 5 5 5 4 20 23 MAX UNITS ns ns ns ns ns ns ns ns ns MHz MHz MHz
TEST CONDITIONS -
Switching Specifications Input tr, tf = 6ns
25oC VCC (V) TYP MAX -40oC TO 85oC MAX -55oC TO 125oC MAX UNITS
PARAMETER HC TYPES Propagation Delay, Clock to Q or Q
SYMBOL
TEST CONDITIONS
tPLH, tPHL
CL = 50pF
2 4.5 6
14 14 65
175 35 30 175 35 30 75 15 13 10 -
220 44 37 220 44 37 95 19 16 10 -
265 53 45 265 53 45 110 22 19 10 -
ns ns ns ns ns ns ns ns ns ns ns pF pF
CL = 15pF Propagation Delay, MR to Q or Q tPLH, tPHL CL = 50pF
5 2 4.5 6
CL = 15pF Output Transition Times tTLH, tTHL CL = 50pF
5 2 4.5 6
Input Capacitance Power Dissipation Capacitance (Notes 3, 4)
CIN CPD
-
5
5
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