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Part: CD54HCT191F3A
Category:
Logic
-> Counters
-> Binary Counters
Description: ti CD54HCT191, High Speed CMOS Logic Presettable Synchronous 4-Bit Binary Up/down Counter
Company: Texas Instruments, Inc.
Datasheet: Download CD54HCT191F3A datasheet File size : 294 kB
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Datasheet text preview:
CD54HC190, CD74HC190 CD54HC191, CD74HC191, CD54HCT191, CD74HCT191 SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
SCHS275E - MARCH 2002 - REVISED OCTOBER 2003
D 2-V to 6-V VCC Operation ('HC190, 191) D 4.5-V to 5.5-V VCC Operation ('HCT191) D Wide Operating Temperature Range of D D D D D D
CD54HC190, 191; CD54HCT191 . . . F PACKAGE CD74HC190 . . . E, NS, OR PW PACKAGE CD74HC191, CD74HCT191 . . . E OR M PACKAGE (TOP VIEW)
-55°C to 125°C Synchronous Counting and Asynchronous Loading Two Outputs for n-Bit Cascading Look-Ahead Carry for High-Speed Counting Balanced Propagation Delays and Transition Times Standard Outputs Drive Up To 15 LS-TTL Loads Significant Power Reduction Compared to LS-TTL Logic ICs
B QB QA CTEN D/U QC QD GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC A CLK RCO MAX/MIN LOAD C D
description/ordering information
The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters. Presetting the counter to the number on preset data inputs (A-D) is accomplished by a low asynchronous parallel load (LOAD) input. Counting occurs when LOAD is high, count enable (CTEN) is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock. ORDERING INFORMATION
TA PACKAGE ORDERABLE PART NUMBER CD74HC190E PDIP - E Tube of 25 Tube of 40 Reel of 2500 SOIC - M -55°C to 125°C Reel of 250 Tube of 40 SOP - NS Reel of 2000 Tube of 90 TSSOP - PW Reel of 2000 Reel of 250 CD74HC191E CD74HCT191E CD74HC191M CD74HC191M96 CD74HC191MT CD74HCT191M CD74HC190NSR CD74HC190PW CD74HC190PWR CD74HC190PWT CD54HC190F3A CDIP - F Tube of 25 CD54HC191F3A CD54HCT191F3A CD54HC190F3A CD54HC191F3A CD54HCT191F3A HJ190 HCT191M HC190M HC191M TOP-SIDE MARKING CD74HC190E CD74HC191E CD74HCT191E
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
CD54HC190, CD74HC190 CD54HC191, CD74HC191, CD54HCT191, CD74HCT191 SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
SCHS275E - MARCH 2002 - REVISED OCTOBER 2003
description/ordering information (continued)
When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO) output, which normally is high, goes low, and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO (see Figure 2). If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3).
FUNCTION TABLE INPUTS LOAD H H L H CTEN L L X H D/U L H X X X X CLK FUNCTION Count up Count down Asynchronous preset No change
D/U or CTEN should be changed only when clock is high. X = Don't care Low-to-high clock transition
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CD54HC190, CD74HC190 CD54HC191, CD74HC191, CD54HCT191, CD74HCT191 SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
SCHS275E - MARCH 2002 - REVISED OCTOBER 2003
'HC190 logic diagram
A 15 B 1
CLK
14
b
5 D/U LOAD 11 c d e f g h i
LOAD DATA T Q
LOAD DATA T Q j
CLKQ FF0
CLKQ FF1
k l m n o 4 CTEN p
3
QA
2
QB
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
CD54HC190, CD74HC190 CD54HC191, CD74HC191, CD54HCT191, CD74HCT191 SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
SCHS275E - MARCH 2002 - REVISED OCTOBER 2003
'HC190 logic diagram (continued)
C 10 b c d e f g h i 12 D 9 13 RCO
MAX/MIN
LOAD DATA j T Q
LOAD DATA T Q
CLK Q FF2
CLK Q FF3
k l m n o p
6
QC
7
QD
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CD54HC190, CD74HC190 CD54HC191, CD74HC191, CD54HCT191, CD74HCT191 SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
SCHS275E - MARCH 2002 - REVISED OCTOBER 2003
'HC191, 'HCT191 logic diagram
A 15 B 1 C 10
14 CLK D/U 5
b c d
11 LOAD
e f g
LOAD DATA T Q
LOAD DATA T Q
LOAD DATA T Q h i
CLK Q FF0
CLKQ FF1
CLKQ FF2
4 CTEN
j k l M N
3
QA
2Q B
6Q C
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
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