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Part: CD74ACT109M
Category:
Logic
-> Flip-Flops
Description: ti CD74ACT109, Dual Positive-edge Triggered J-k Flip-flops With Set And Reset
Company: Texas Instruments, Inc.
Datasheet: Download CD74ACT109M datasheet File size : 283 kB
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Datasheet text preview:
CD54ACT109, CD74ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCHS327 JANUARY 2003
D D D D D D
Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015
CD54ACT109 . . . F PACKAGE CD74ACT109 . . . E OR M PACKAGE (TOP VIEW)
1CLR 1J 1K 1CLK 1PRE 1Q 1Q GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC 2CLR 2J 2K 2CLK 2PRE 2Q 2Q
description/ordering information
The 'ACT109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together. ORDERING INFORMATION
TA PDIP E 55°C to 125°C to 125°C SOIC M PACKAGE Tube Tube Tape and reel ORDERABLE PART NUMBER CD74ACT109E CD74ACT109M CD74ACT109M96 TOP-SIDE MARKING CD74ACT109E ACT109M
CDIP F Tube CD54ACT109F3A CD54ACT109F3A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each flip-flop) INPUTS PRE L H L H H H H CLR H L L H H H H CLK X X X J X X X L H L H K X X X L L H H H OUTPUTS Q H L H L Toggle Q0 Q0 L Q L H H H
H H L X X Q0 Q0 Unpredictable and unstable condition if both PRE and CLR go high simultaneously after both being low at the same time
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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1
CD54ACT109, CD74ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCHS327 JANUARY 2003
logic diagram, each flip-flop (positive logic)
PRE C C TG TG K C C C CLK C TG C C CLR C Q TG C Q
J
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6 V Input clamp current, IIK (VI VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO > 0 V or VO < VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
TA = 25°C MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 0 4.5 2 0.8 VCC VCC 24 24 10 0 0 MAX 5.5 55°C to 125°C MIN 4.5 2 0.8 VCC VCC 24 24 10 0 0 MAX 5.5 40°C to 85°C MIN 4.5 2 0.8 VCC VCC 24 24 10 MAX 5.5 V V V V V mA mA ns/V UNIT
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CD54ACT109, CD74ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCHS327 JANUARY 2003
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = 50 µA IOH = 24 mA IOH = 50 mA IOH = 75 mA IOL = 50 µA IOL = 24 mA IOL = 50 mA IOL = 75 mA II ICC VI = VCC or GND VI = VCC or GND, VI = VCC 2.1 V IO = 0 VCC 4.5 V 4.5 V 5.5 V 5.5 V 4.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 4.5 V to 5.5 V ±0.1 4 2.4 ±1 80 3 0.1 0.36 0.1 0.5 1.65 1.65 ±1 40 2.8 µA µA mA TA = 25°C MIN 4.4 3.94 MAX 55°C to 125°C MIN 4.4 3.7 3.85 3.85 0.1 0.44 V MAX 40°C to 85°C MIN 4.4 3.8 V MAX UNIT
VOH
VI = VIH or VIL or
VOL
VI = VIH or VIL or
DICC
Ci 10 10 10 pF Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50- transmission-line drive capability at 85°C and 75- transmission-line drive capability at 125°C. Additional quiescent supply current per input pin, TTL inputs high, 1 unit load ACT INPUT LOAD TABLE INPUT J or CLK K CLR or PRE UNIT LOAD 1 0.53 0.58
Unit Load is ICC limit specified in electrical characteristics table (e.g., 2.4 mA at 25°C).
timing requirements over recommended operating conditions (unless otherwise noted)
55°C to 125°C MIN fclock tw tsu th trec Clock frequency Pulse duration duration Setup time, before CLK Hold time, after CLK Recovery time, before CLK CLK high or low CLR or PRE low J or K J or K CLR or PRE 5 5.5 5.5 0 2.5 MAX 100 4.4 4.8 4.8 0 2.2 40°C to 85°C MIN MAX 114 MHz ns ns ns ns UNIT
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
CD54ACT109, CD74ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCHS327 JANUARY 2003
switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL CLK CLR or PRE CLK CLR or PRE Q or Q Q or Q or FROM (INPUT) TO (OUTPUT) 55°C to 125°C MIN 100 2.6 3.1 2.6 3.1 10.3 12.2 10.3 12.2 MAX 40°C to 85°C MIN 114 2.7 3.2 2.7 3.2 9.4 11.1 9.4 11.1 MAX MHz ns ns UNIT
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER Cpd Power dissipation capacitance TYP 56 UNIT pF
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CD54ACT109, CD74ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCHS327 JANUARY 2003
PARAMETER MEASUREMENT INFORMATION
R1 = 500 S1 2 × VCC Open GND R2 = 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 × VCC GND
From Output Under Test CL = 50 pF (see Note A)
tw 3V LOAD CIRCUIT Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATION 3V 1.5 V 0V tsu Data Input 1.5 V 10% 90% tr th 90% 3V 1.5 V 10% 0 V tf 1.5 V 0V
CLR Input
3V 1.5 V 0V trec 3V
Reference Input
CLK
1.5 V 0V VOLTAGE WAVEFORMS RECOVERY TIME 3V
VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES
Input
1.5 V tPLH
1.5 V 0V tPHL 90% tr 90% VOH 50% VCC 10% VOL tf 90% tr VOH VOL
Output Control tPZL
3V 1.5 V 1.5 V 0V tPLZ 20% VCC tPZH VCC 20% VCC VOL tPHZ 80% VCC VOH 80% VCC 0 V
In-Phase Output
50% 10% tPHL
Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B)
tPLH 50% VCC 10% tf 50% 10%
Out-of-Phase Output
90%
VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. I. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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