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Part: CD74ACT10E
Category:
Logic
-> Gates
-> NAND Gates
Description: ti CD74ACT10, Triple 3-Input NAND Gates
Company: Texas Instruments, Inc.
Datasheet: Download CD74ACT10E datasheet File size : 283 kB
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Datasheet text preview:
CD74ACT10 TRIPLE 3-INPUT POSITIVE-NAND GATES
SCHS316 NOVEMBER 2002
D Inputs Are TTL-Voltage Compatible D Speed of Bipolar F, AS, and S, With D D D D
Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current Fanout to 15 F Devices SCR Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015
E OR M PACKAGE (TOP VIEW)
1A 1B 2A 2B 2C 2Y GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 1C 1Y 3C 3B 3A 3Y
description/ordering information
The CD74ACT10 contains three independent 3-input NAND gates. The device performs the Boolean functions Y = A · B · C or Y = A + B + C in positive logic. ORDERING INFORMATION
TA PDIP E 55°C to 125°C SOIC M PACKAGE Tube Tube Tape and Reel ORDERABLE PART NUMBER CD74ACT10E CD74ACT10M CD74ACT10M96 TOP-SIDE MARKING CD74ACT10E ACT10M
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS A H L X X B H X L X C H X X L OUTPUT Y L H H H
logic diagram, each gate (positive logic)
A B C Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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CD74ACT10 TRIPLE 3-INPUT POSITIVE-NAND GATES
SCHS316 NOVEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6 V Input clamp current, IIK (VI VCC) ( see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) ( see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
TA = 25°C MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 0 4.5 2 0.8 VCC VCC 24 24 10 0 0 MAX 5.5 55°C to 125°C MIN 4.5 2 0.8 VCC VCC 24 24 10 0 0 MAX 5.5 40°C to 85°C MIN 4.5 2 0.8 VCC VCC 24 24 10 MAX 5.5 V V V V V mA mA ns/V UNIT
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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CD74ACT10 TRIPLE 3-INPUT POSITIVE-NAND GATES
SCHS316 NOVEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = 50 µA IOH = 24 mA IOH = 50 mA IOH = 75 mA IOL = 50 µA IOL = 24 mA IOL = 50 mA IOL = 75 mA II ICC DICC VI = VCC or GND VI = VCC or GND, VI = VCC 2.1 V IO = 0 VCC 4.5 V 4.5 V 5.5 V 5.5 V 4.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 4.5 V to 5.5 V ±0.1 4 2.4 ±1 80 3 0.1 0.36 0.1 0.5 1.65 1.65 ±1 40 2.8 µA µA mA TA = 25°C MIN 4.4 3.94 MAX 55°C to 125°C MIN 4.4 3.7 3.85 3.85 0.1 0.44 V MAX 40°C to 85°C MIN 4.4 3.8 V MAX UNIT
VOH
VI = VIH or VIL or
VOL
VI = VIH or VIL or
Ci 10 10 10 pF Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50- transmission-line drive capability at 85°C and 75- transmission-line drive capability at 125°C. Additional quiescent supply current per input pin, TTL inputs high, 1 unit load ACT INPUT LOAD TABLE INPUT A, B, or C UNIT LOAD 0.19
Unit load is ICC limit specified in electrical characteristics table (e.g., 2.4 mA at 25°C).
switching characteristics over recommended operating free-air temperature range, VCC = 5 V " 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL FROM (INPUT) TO (OUTPUT) 55°C to 125°C MIN 3.4 A, B or C B, or Y 3.4 MAX 13.5 13.5 40°C to 85°C MIN 3.5 3.5 MAX 12.3 12.3 ns UNIT
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER Cpd Power dissipation capacitance TYP 50 UNIT pF
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3
CD74ACT10 TRIPLE 3-INPUT POSITIVE-NAND GATES
SCHS316 NOVEMBER 2002
PARAMETER MEASUREMENT INFORMATION
R1 = 500 S1 2 × VCC Open GND R2 = 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 × VCC GND
From Output Under Test CL = 50 pF (see Note A)
tw 3V LOAD CIRCUIT Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATION 3V 1.5 V 0V tsu Data Input 1.5 V 10% 90% tr th 90% 3V 1.5 V 10% 0 V tf 1.5 V 0V
CLR Input
3V 1.5 V 0V trec 3V
Reference Input
CLK
1.5 V 0V VOLTAGE WAVEFORMS RECOVERY TIME 3V
VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES
Input
1.5 V tPLH
1.5 V 0V tPHL 90% tr 90% VOH 50% VCC 10% VOL tf 90% tr VOH VOL
Output Control tPZL
3V 1.5 V 1.5 V 0V tPLZ 20% VCC tPZH VCC 20% VCC VOL tPHZ 80% VCC VOH 80% VCC 0 V
In-Phase Output
50% 10% tPHL
Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B)
tPLH 50% VCC 10% tf 50% 10%
Out-of-Phase Output
90%
VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis.
Figure 1. Load Circuit and Voltage Waveforms
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MECHANICAL
MPDI002C JANUARY 1995 REVISED DECEMBER 20002
N (R-PDIP-T**)
16 PINS SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
PINS ** DIM A 16 9 A MAX
14 0.775 (19,69) 0.745 (18,92)
16 0.775 (19,69) 0.745 (18,92)
18 0.920 (23,37) 0.850 (21,59)
20 1.060 (26,92) 0.940 (23,88)
A MIN
0.260 (6,60) 0.240 (6,10)
C
MS-100 VARIATION
AA
BB
AC
AD
1 0.070 (1,78) MAX
8
0.035 (0,89) MAX
0.020 (0,51) MIN
0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gauge Plane
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M
0.430 (10,92) MAX
14/18 PIN ONLY 20 pin vendor option
D 4040049/E 12/2002
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
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