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Part: CD74ACT138
Category:
Logic
-> Decoder/Demultiplexers
-> CMOS/BiCMOS->AC/ACT Family
Description: 3-to-8-line Decoders/demultiplexers
Company: Texas Instruments, Inc.
Datasheet: Download CD74ACT138 datasheet File size : 283 kB
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Datasheet text preview:
CD54ACT138, CD74ACT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCHS329A JANUARY 2003 REVISED FEBRUARY 2003
D D D D D D D D
Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception Balanced Propagation Delays ±24-mA Output Drive Current Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015
CD54ACT138 . . . F PACKAGE CD74ACT138 . . . E OR M PACKAGE (TOP VIEW)
A B C G2A G2B G1 Y7 GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6
description/ordering information
The 'ACT138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications (see Application Information). ORDERING INFORMATION
TA PDIP E 55°C to 125°C to 125°C SOIC M PACKAGE Tube Tube Tape and reel ORDERABLE PART NUMBER CD74ACT138E CD74ACT138M CD74ACT138M96 TOP-SIDE MARKING CD74ACT138E ACT138M
CDIP F Tube CD54ACT138F3A CD54ACT138F3A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
CD54ACT138, CD74ACT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCHS329A JANUARY 2003 REVISED FEBRUARY 2003
FUNCTION TABLE ENABLE INPUTS G1 X X L H H H H H H H H G2A H X X L L L L L L L L G2B X H X L L L L L L L L SELECT INPUTS C X X X L L L L H H H H B X X X L L H H L L H H A X X X L H L H L H L H Y0 H H H L H H H H H H H Y1 H H H H L H H H H H H Y2 H H H H H L H H H H H OUTPUTS Y3 H H H H H H L H H H H Y4 H H H H H H H L H H H Y5 H H H H H H H H L H H Y6 H H H H H H H H H L H Y7 H H H H H H H H H H L
logic diagram (positive logic)
15 A 1 14 Y1 Y0
13 Select Inputs B 2 12
Y2
Y3 Data Outputs Y4
11 3 C 10
Y5
9
Y6
G2A Enable Inputs G2B G1
4 5 6
7
Y7
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CD54ACT138, CD74ACT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCHS329A JANUARY 2003 REVISED FEBRUARY 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6 V Input clamp current, IIK (VI VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO > 0 V or VO < VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
TA = 25°C MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 0 4.5 2 0.8 VCC VCC 24 24 10 0 0 MAX 5.5 55°C to 125°C MIN 4.5 2 0.8 VCC VCC 24 24 10 0 0 MAX 5.5 40°C to 85°C MIN 4.5 2 0.8 VCC VCC 24 24 10 MAX 5.5 V V V V V mA mA ns/V UNIT
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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CD54ACT138, CD74ACT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCHS329A JANUARY 2003 REVISED FEBRUARY 2003
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = 50 µA IOH = 24 mA IOH = 50 mA IOH = 75 mA IOL = 50 µA IOL = 24 mA IOL = 50 mA IOL = 75 mA II ICC VI = VCC or GND VI = VCC or GND, VI = VCC 2.1 V IO = 0 VCC 4.5 V 4.5 V 5.5 V 5.5 V 4.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 4.5 V to 5.5 V ±0.1 8 2.4 ±1 160 3 0.1 0.36 0.1 0.5 1.65 1.65 ±1 80 2.8 µA µA mA TA = 25°C MIN 4.4 3.94 MAX 55°C to 125°C MIN 4.4 3.7 3.85 3.85 0.1 0.44 V MAX 40°C to 85°C MIN 4.4 3.8 V MAX UNIT
VOH
VI = VIH or VIL or
VOL
VI = VIH or VIL or
DICC
Ci 10 10 10 pF Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50- transmission-line drive capability at 85°C and 75- transmission-line drive capability at 125°C. Additional quiescent supply current per input pin, TTL inputs high, 1 unit load ACT INPUT LOAD TABLE INPUT A, B, or C G2A or G2B G1 UNIT LOAD 0.83 1 0.42
Unit Load is ICC limit specified in electrical characteristics table (e.g., 2.4 mA at 25°C).
switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) 55°C to 125°C MIN 3 3 2.8 2.8 2.6 2.6 MAX 12 12 11 11 10.5 10.5 40°C to 85°C MIN 3.1 3.1 2.8 2.8 2.7 2.7 MAX 10.9 10.9 10 10 9.5 9.5 ns ns ns UNIT
A, B C B,
Any Y Any Y Any Y
G1 G2A, G2B G2B
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER Cpd Power dissipation capacitance TYP 110 UNIT pF
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CD54ACT138, CD74ACT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCHS329A JANUARY 2003 REVISED FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
R1 = 500 S1 2 × VCC Open GND R2 = 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 × VCC GND
From Output Under Test CL = 50 pF (see Note A)
tw 3V LOAD CIRCUIT Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATION 3V 1.5 V 0V tsu Data Input 1.5 V 10% 90% tr th 90% 3V 1.5 V 10% 0 V tf 1.5 V 0V
CLR Input
3V 1.5 V 0V trec 3V
Reference Input
CLK
1.5 V 0V VOLTAGE WAVEFORMS RECOVERY TIME 3V
VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES
Input
1.5 V tPLH
1.5 V 0V tPHL 90% tr 90% VOH 50% VCC 10% VOL tf 90% tr VOH VOL
Output Control tPZL
3V 1.5 V 1.5 V 0V tPLZ 20% VCC tPZH VCC 20% VCC VOL tPHZ 80% VCC VOH 80% VCC 0 V
In-Phase Output
50% 10% tPHL
Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B)
tPLH 50% VCC 10% tf 50% 10%
Out-of-Phase Output
90%
VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. I. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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