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Part: CD74FCT244M96
Category:
Logic
-> Buffers/Drivers
-> Non-Inverting Buffers and Drivers
Description: ti CD74FCT244, Bicmos FCT Interface Logic Octal Non-inverting Buffers/line Drivers With 3-State Outputs
Company: Texas Instruments, Inc.
Datasheet: Download CD74FCT244M96 datasheet File size : 283 kB
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Datasheet text preview:
CD74FCT244, CD74FCT244AT BiCMOS OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS
SCBS722B JULY 2000 REVISED AUGUST 2003
D D D D D D D D
BiCMOS Technology With Low Quiescent Power Buffered Inputs Noninverted Outputs Input/Output Isolation From VCC Controlled Output Edge Rates 64-mA Output Sink Current Output Voltage Swing Limited to 3.7 V SCR Latch-Up-Resistant BiCMOS Process and Circuit Design
CD74FCT244 . . . E, M, OR SM PACKAGE CD74FCT244AT . . . E OR M PACKAGE (TOP VIEW)
description/ordering information
1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
The CD74FCT244 and CD74FCT244AT are octal buffer/line drivers with 3-state outputs using a small-geometry BiCMOS technology. The output stages are a combination of bipolar and CMOS transistors that limit the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces the power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 64 mA. These devices are organized as two 4-bit buffers/line drivers with separate active-low output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION
TA PACKAGE PDIP E SOIC M 0°C to 70 C 70°C SSOP SM PDIP E SOIC M Tube Tube Tape and reel Tape and reel Tube Tube Tape and reel ORDERABLE PART NUMBER CD74FCT244E CD74FCT244M CD74FCT244M96 CD74FCT244SM96 CD74FCT244ATE CD74FCT244ATM CD74FCT244ATM96 TOP-SIDE MARKING CD74FCT244E 74FCT244M FCT244SM CD74FCT244ATE 74FCT244ATM
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each buffer/driver) INPUTS OE L L H A H L X OUTPUT Y H L Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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1
CD74FCT244, CD74FCT244AT BiCMOS OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS
SCBS722B JULY 2000 REVISED AUGUST 2003
logic diagram (positive logic)
1OE 1 2OE 19
1A1
2
18
1Y1
2A1
11
9
2Y1
1A2
4
16
1Y2
2A2
13
7
2Y2
1A3
6
14
1Y3
2A3
15
5
2Y3
1A4
8
12
1Y4
2A4
17
3
2Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
DC supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6 V DC input clamp current, IIK (VI < 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA DC output clamp current, IOK (VO < 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA DC output sink current per output pin, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA DC output source current per output pin, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Continuous current through VCC, ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 mA Continuous current through GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 mA Package thermal impedance, JA (see Note 1): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W SM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate (slew rate) 0 0 4.75 2 0.8 VCC VCC 15 64 10 MAX 5.25 UNIT V V V V V mA mA ns/V
TA Operating free-air temperature 0 70 °C NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
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CD74FCT244, CD74FCT244AT BiCMOS OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS
SCBS722B JULY 2000 REVISED AUGUST 2003
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL II IOZ IOS ICC ICC Ci Co II = 18 mA IOH = 15 mA IOL = 64 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND, VI = VCC or GND, One input at 3.4 V, VI = VCC or GND VO = VCC or GND VO = 0 IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC 4.75 V 4.75 V 4.75 V 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V 60 8 1.6 10 15 2.4 0.55 ±0.1 ±0.5 60 80 1.6 10 15 TA = 25°C MIN MAX 1.2 2.4 0.55 ±1 ±10 MIN MAX 1.2 UNIT V V V
mA mA
mA
mA
mA pF pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 100 ms. This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
switching characteristics over recommended operating VCC = 5 V ± 0.25 V (unless otherwise noted) (see Figure 1)
CD74FCT244 PARAMETER FROM (INPUT) A OE OE TO (OUTPUT) Y Y Y TA = 25°C TYP 4.5 6 5 MIN 1.5 1.5 1.5
free-air
temperature
CD74FCT244AT
range,
MAX 6.5 8 7
TA = 25°C TYP 3.8 4.8 4.5
MIN 1.5 1.5 1.5
MAX 5.3 6.5 5.8
UNIT
tpd ten tdis
ns ns ns
noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C
PARAMETER VOL(P) VOH(V) VIH(D) VIL(D) Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage Low-level dynamic input voltage 2 0.8 MIN TYP 1 0.5 MAX UNIT V V V V
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load, f = 1 MHz TYP 35 UNIT pF
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3
CD74FCT244, CD74FCT244AT BiCMOS OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS
SCBS722B JULY 2000 REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
7V From Output Under Test CL = 50 pF (see Note A) Test Point 500 From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS S1 Open 7V Open 7V
1.5 V 10%
90%
90%
3V 1.5 V 10% 0 V tf 3V Timing Input 1.5 V 0V 3V tsu Data Input 0V 1.5 V th 3V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 3V 1.5 V tPZL VOH Output Waveform 1 (see Note B) tPZH VOH Output Waveform 2 (see Note B) 1.5 V 1.5 V 1.5 V 0V tPLZ 3.5 V VOL + 0.3 V VOL tPHZ V VOH 0.3 V OH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
tr VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES tw
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS PULSE DURATION
Input tPLH In-Phase Output tPHL Out-of-Phase Output
1.5 V
1.5 V 0V tPHL 1.5 V 1.5 V VOL tPLH 1.5 V 1.5 V VOL
Output Control
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr and tf = 2.5 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
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MECHANICAL
MPDI002C JANUARY 1995 REVISED DECEMBER 20002
N (R-PDIP-T**)
16 PINS SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
PINS ** DIM A 16 9 A MAX
14 0.775 (19,69) 0.745 (18,92)
16 0.775 (19,69) 0.745 (18,92)
18 0.920 (23,37) 0.850 (21,59)
20 1.060 (26,92) 0.940 (23,88)
A MIN
0.260 (6,60) 0.240 (6,10)
C
MS-100 VARIATION
AA
BB
AC
AD
1 0.070 (1,78) 0.045 (1,14) D
8
0.045 (1,14) 0.030 (0,76) D
0.020 (0,51) MIN
0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gauge Plane
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M
0.430 (10,92) MAX
14/18 PIN ONLY 20 pin vendor option
D 4040049/E 12/2002
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
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