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Part: CD74HC251E
Category:
Logic
-> Encoders/Multiplexers
-> Multiplexers
Description: ti CD74HC251, High Speed CMOS Logic 8-Input Multiplexer With 3-State Outputs
Company: Texas Instruments, Inc.
Datasheet: Download CD74HC251E datasheet File size : 294 kB
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Datasheet text preview:
CD54HC251, CD74HC251, CD54HCT251, CD74HCT251
Data sheet acquired from Harris Semiconductor SCHS169C
November 1997 - Revised October 2003
High-Speed CMOS Logic 8-Input Multiplexer, Three-State
Description
The 'HC251 and 'HCT251 are 8-channel digital multiplexers with three-state outputs, fabricated with high-speed silicongate CMOS technology. Together with the low power consumption of standard CMOS integrated circuits, they possess the ability to drive 10 LSTTL loads. The three-state feature makes them ideally suited for interfacing with bus lines in a bus-oriented system. This multiplexer features both true (Y) and complement (Y) outputs as well as an output enable (OE) input. The OE must be at a low logic level to enable this device. When the OE input is high, both outputs are in the high-impedance state. When enabled, address information on the data select inputs determines which data input is routed to the Y and Y outputs. The 'HCT251 logic family is speed, function, and pin-compatible with the standard 'LS251.
Features
· Selects One of Eight Binary Data Inputs
[ /Title (CD74 HC251 , CD74 HCT25 1) /Subject (High Speed CMOS Logic 8-Input Multiplexer; Three-
· Three-State Output Capability · True and Complement Outputs · Typical (Data to Output) Propagation Delay of 14ns at VCC = 5V, CL = 15pF, TA = 25oC · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · Alternate Source is Philips · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC251F3A CD54HCT251F3A CD74HC251E CD74HC251M CD74HC251MT CD74HC251M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC
Pinout
CD54HC251, CD54HCT251 (CERDIP) CD74HC251, CD74HCT251 (PDIP, SOIC) TOP VIEW
I3 1 I2 2 I1 3 I0 4 Y5 Y6 OE 7 GND 8 16 VCC 15 I4 14 I5 13 I6 12 I7 11 S0 10 S1 9 S2
CD74HCT251E CD74HCT251M CD74HCT251MT CD74HCT251M96
NOTE: When ordering, use the entire par t number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
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CD54HC251, CD74HC251, CD54HCT251, CD74HCT251 Functional Diagram
OE 7 I0 I1 I2 CHANNEL INPUTS I3 I4 I5 I6 I7 S0 4 3 2 1 15 14 5 13 12 11 6 Y OUTPUTS Y
10 DATA S1 SELECT 9 S2
TRUTH TABLE INPUTS SELECT S2 X L L L L H H H H S1 X L L H H L L H H S0 X L H L H L H L H OUTPUT CONTROL OE H L L L L L L L L Y Z I0 I1 I2 I3 I4 I5 I6 I7 Y Z I0 I1 I2 I3 I4 I5 I6 I7 OUTPUT
H = High Voltage Level, L = Low Voltage Level, X = Don't Care, Z = High Impedance (Off), I0, I1...I7 = the level of the respective input.
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CD54HC251, CD74HC251, CD54HCT251, CD74HCT251
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 -0.02 -0.02 High Level Output Voltage TTL Loads -4 -5.2 Low Level Output Voltage CMOS Loads VOL VIH or VIL 0.02 0.02 0.02 Low Level Output Voltage TTL Loads 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 V V V V V V V V V V V V V V V V V V SYMBOL VI (V) IO (mA) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
VCC (V)
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CD54HC251, CD74HC251, CD54HCT251, CD74HCT251
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER Input Leakage Current Quiescent Device Current Three-State Leakage Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Three-State Leakage Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC VCC and GND VCC or GND VIL or VIH VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL II ICC VI (V) VCC or GND VCC or GND VIL or VIH IO (mA) 0 VO = VCC or GND 25oC MIN TYP MAX ±0.1 8 ±0.5 -40oC TO 85oC -55oC TO 125oC MIN MAX ±1 80 ±5.0 MIN MAX ±1 160 ±10 UNITS µA µA µA
VCC (V) 6 6 6
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 VO = VCC or GND -
5.5 5.5 6
-
±0.1 8 ±0.5
-
±1 80 ±5.0
-
±1 160 ±10
µA µA µA
ICC (Note 2)
VCC -2.1
4.5 to 5.5
-
100
360
-
450
-
490
µA
HCT Input Loading Table
INPUT S0, S1, S2 I0 - I7 OE UNIT LOADS 0.55 0.5 2.65
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC.
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CD54HC251, CD74HC251, CD54HCT251, CD74HCT251
Switching Specifications Input tr, tf = 6ns
TEST CONDITIONS 25oC VCC (V) MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
PARAMETER HC TYPES Propagation Delay Select to Outputs
SYMBOL
tPLH, tPHL CL = 50pF
2 4.5
-
21 12 11 60
245 49 42 175 35 30 140 28 24 75 15 13 10 15 -
-
305 61 52 220 44 37 175 35 30 95 19 16 10 15 -
-
370 74 63 265 53 45 210 42 36 110 22 19 10 15 -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF pF
CL =15pF CL = 50pF Data to Outputs tPLH, tPHL CL = 50pF
5 6 2 4.5
CL =15pF CL = 50pF Enable to High Z and Enable from High Z tPLH, tPHL CL = 50pF
5 6 2 4.5
CL =15pF CL = 50pF Output Transition Time tTLH, tTHL CL = 50pF
5 6 2 4.5 6
Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes 3, 4) HCT TYPES Propagation Delay Select to Outputs
CIN CO CPD
-
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tPLH, tPHL CL = 50pF CL =15pF 4.5 5 4.5 5 4.5 5 4.5 5 12 60 18 12 42 35 30 15 10 44 38 19 10 53 63 53 45 22 10 ns ns ns ns ns ns ns pF pF
Data to Outputs
tPLH, tPHL CL = 50pF CL =15pF
Enable to High Z and Enable tPLH, tPHL CL = 50pF from High Z CL =15pF Output Transition Time Input Capacitance Power Dissipation Capacitance (Notes 3, 4) NOTES: tTLH, tTHL CL = 50pF CIN CPD -
3. CPD is used to determine the dynamic power consumption, per package. 4. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
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