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Part: CD74HC253MT
Category:
Logic
-> Encoders/Multiplexers
-> Multiplexers
Description: ti CD74HC253, High Speed CMOS Logic Dual 4-Input Multiplexers
Company: Texas Instruments, Inc.
Datasheet: Download CD74HC253MT datasheet File size : 294 kB
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Datasheet text preview:
CD74HC253, CD74HCT253
Data sheet acquired from Harris Semiconductor SCHS170B
November 1997 - Revised October 2003
High-Speed CMOS Logic Dual 4-Input Multiplexer
Description
The CD74HC253 and CD74HCT253 are dual 4-to-1 line selector/multiplexers having three-state outputs. One of four sources for each section is selected by the common select inputs, S0 and S1. When the output enable (1OE, 2OE) is HIGH, the output is in the high-impedance state.
Features
· Common Select Inputs
[ /Title (CD74 HC253 , CD74 HCT25 3) /Subject (High Speed CMOS Logic Dual 4-Input Multiplexer)
· Separate Output-Enable Inputs · Three-State Outputs · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD74HC253E CD74HC253M CD74HC253MT CD74HC253M96 CD74HCT253E CD74HCT253M CD74HCT253MT CD74HCT253M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC
NOTE: When ordering, use the entire par t number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250.
Pinout
CD74HC253, CD74HCT253 (PDIP, SOIC) TOP VIEW
1OE 1 S1 2 1I3 3 1I2 4 1I1 5 1I0 6 1Y 7 GND 8 16 VCC 15 2OE 14 S0 13 2I3 12 2I2 11 2I1 10 2I0 9 2Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
1
© 2003, Texas Instruments Incorporated
1
CD74HC253, CD74HCT253 Functional Diagrams
2OE
15
2I3
13
2I2
12
2I1
11
2I0
10
S0
14
S1
2
1I0
6
1I1
5
1I2
4
1I3
3
1OE
1
2OE 2OE 1OE
1OE
16
VCC
8 GND
P 2OE 9 2Y
N 2OE
N 1OE 1Y
P 1OE 7
TRUTH TABLE SELECT INPUTS (Note 1) S1 X L L L L H H H H S0 X L L H H L L H H I0 X L H X X X X X X OUTPUT ENABLE I3 X X X X X X X L H OE H L L L L L L L L
DATA INPUTS I1 X X X L H X X X X I2 X X X X X L H X X
OUTPUT Y Z L H L H L H L H
H = High Voltage Level, L = Low Voltage Level, X = Don't Care, Z = High Impedance (Off). NOTE: 1. Select inputs S1 and S0 are common to both sections.
2
CD74HC253, CD74HCT253
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -6 -7.8 0.02 0.02 0.02 -6 -7.8 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 V V V V V V V V V V V V V V V V V V µA SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
3
CD74HC253, CD74HCT253
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER Quiescent Device Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load Three-State Leakage Current NOTE: 3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 3) IOZ VCC and GND VCC or GND VCC -2.1 VIL or VIH VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL ICC VI (V) VCC or GND IO (mA) 0 VCC (V) 6 25oC MIN TYP MAX 8 -40oC TO 85oC -55oC TO 125oC MIN MAX 80 MIN MAX 160 UNITS µA
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5 5.5
-
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
VO = VCC or GND
-
-
±0.5
-
±5
-
±10
µA
HCT Input Loading Table
INPUT 1IO - 1I3, 2IO-2l3 1EO, 2EO, S0, S1 UNIT LOADS 0.4 1
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
TEST SYMBOL CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
PARAMETER HC TYPES Propagation Delay Select to Outputs
tPLH, tPHL
CL = 50pF
2 4.5
-
14 -
175 35 30
-
220 44 37
-
265 53 45
ns ns ns ns
CL =15pF CL = 50pF
5 6
4
CD74HC253, CD74HCT253
Switching Specifications Input tr, tf = 6ns (Continued)
TEST SYMBOL CONDITIONS tPLH, tPHL CL = 50pF VCC (V) 2 4.5 CL =15pF CL = 50pF Disable Delay Times tPHZ, tPLZ CL = 50pF CL = 50pF CL = 15pF CL = 50pF Enable Delay Times tPZH, tPZL CL = 50pF CL = 50pF CL = 15pF CL = 50pF Output Transition Times tTLH, tTHL CL = 50pF 5 6 2 4.5 5 6 2 4.5 5 6 2 4.5 6 Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes 4, 5) HCT TYPES Propagation Delay Select to Outputs tPLH, tPHL CL = 50pF CL =15pF Data to Outputs tPLH, tPHL tPLH, tPHL tPZH, tPZL CL = 50pF CL =15pF CL = 50pF CL =15pF CL = 50pF CL =15pF 4.5 5 4.5 5 4.5 5 4.5 5 4.5 5 12 12 52 16 16 40 38 30 30 12 10 20 48 38 38 15 10 20 50 60 57 45 45 18 10 20 ns ns ns ns ns ns ns ns ns pF pF pF CI CO CPD 5 25oC MIN TYP 14 12 9 46 MAX 175 35 30 150 30 26 110 22 19 60 12 10 10 20 -40oC TO 85oC MIN MAX 220 44 37 190 38 33 140 28 24 75 15 13 10 20 -55oC TO 125oC MIN MAX 265 53 45 225 45 38 165 33 28 90 18 15 10 20 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF pF
PARAMETER Data to Outputs
Disable Delay Times
Enable Delay Times
Output Transition Time Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes 4, 5) NOTES:
tTLH, tTHL CL = 50pF CIN CO CPD -
4. CPD is used to determine the dynamic power consumption, per multiplexer. 5. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
5
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