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Part: CD74HC259E
Category:
Logic
-> Latches
Description: ti CD74HC259, High Speed CMOS Logic 8-Bit Addressable Latch
Company: Texas Instruments, Inc.
Datasheet: Download CD74HC259E datasheet File size : 173 kB
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Datasheet text preview:
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
Data sheet acquired from Harris Semiconductor SCHS173C
November 1997 - Revised October 2003
High-Speed CMOS Logic 8-Bit Addressable Latch
Description
The 'HC259 and 'HCT259 Addressable Latch features the low-power consumption associated with CMOS circuitr y and has speeds comparable to low-power Schottky. This latches three active modes and one reset mode. When both the Latch Enable (LE) and Master Reset (MR) inputs are low (8-line Demultiplexer mode) the output of the addressed latch follows the Data input and all other outputs are forced low. When both MR and LE are high (Memory Mode), all outputs are isolated from the Data input, i.e., all latches hold the last data presented before the LE transition from low to high. A condition of LE low and MR high (Addressable Latch mode) allows the addressed latch's output to follow the data input; all other latches are unaffected. The Reset mode (all outputs low) results when LE is high and MR is low.
Features
· Buffered Inputs and Outputs
[ /Title (CD74 HC259 , CD74 HCT25 9) /Subject (High Speed CMOS Logic 8-Bit Addres sable Latch)
· Four Operating Modes · Typical Propagation Delay of 15ns at VCC = 5V, CL = 15pF, TA = 25oC · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC259F3A CD54HCT259F3A CD74HC259E CD74HC259M CD74HC259MT CD74HC259M96 CD74HCT259E CD74HCT259M CD74HCT259MT CD74HCT259M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC
NOTE: When ordering, use the entire par t number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
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CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Pinout
CD54HC259, CD54HCT259 (CERDIP) CD74HC259, CD74HCT259 (PDIP, SOIC) TOP VIEW
A0 1 A1 2 A2 3 Q0 4 Q1 5 Q2 6 Q3 7 GND 8 16 VCC 15 MR 14 LE 13 D 12 Q7 11 Q6 10 Q5 9 Q4
Functional Diagram
4 1 A0 2 A1 3 9 14 15 MR 13 D 10 11 12 1-OF-8 DECODER 8 LATCHES 5 6 7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
A2
LE
GND = 8 VCC = 16
TRUTH TABLE INPUTS MR H LE L OUTPUT OF ADDRESS LATCH D
LATCH SELECTION TABLE SELECT INPUTS LATCH ADDRESSED 0 1 2 3 4 5 6 7
EACH OTHER OUTPUT Qio Qio L
FUNCTION Addressable Latch Memory 8-Line Demultiplexer Reset
A2 L L L
A1 L L H H L L H H
A0 L H L H L H L H
H L
H L
Qio D
L H H
L
H
L
L
H H
H = High Voltage Level L = Low Voltage Level D = The level at the data input Qio = The level of Qi (i = 0, 1...7, as appropriate) before the indicated steady-state input conditions were established.
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CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 V V V V V V V V V V V V V V V V V V µA SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
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CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER Quiescent Device Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 2) VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL ICC VI (V) VCC or GND IO (mA) 0 VCC (V) 6 25oC MIN TYP MAX 8 -40oC TO 85oC -55oC TO 125oC MIN MAX 80 MIN MAX 160 UNITS µA
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
HCT Input Loading Table
INPUT A0 - A2, LE D MR UNIT LOADS 1.5 1.2 0.75
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC.
Prerequisite for Switching Specifications
25oC PARAMETER HC TYPES Pulse Width LE tWL 2 4.5 6 70 14 12 90 18 15 105 21 18 ns ns ns SYMBOL VCC (V) MIN TYP MAX -40oC TO 85oC MIN TYP MAX -55oC TO 125oC MIN TYP MAX UNITS
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CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
Prerequisite for Switching Specifications (Continued)
25oC PARAMETER MR SYMBOL tWL VCC (V) 2 4.5 6 Setup Time D to LE A to LE tSU 2 4.5 6 Hold Time D to LE A to LE tH 2 4.5 6 HCT TYPES Pulse Width LE MR Setup Time D to LE A to LE Hold Time D to LE A to LE tWL 4.5 18 23 27 ns 0 0 0 0 0 0 0 0 0 ns ns ns 80 16 14 100 20 17 120 24 20 ns ns ns MIN 70 14 12 TYP MAX -40oC TO 85oC MIN 90 18 15 TYP MAX -55oC TO 125oC MIN 105 21 18 TYP MAX UNITS ns ns ns
tSU
4.5
17
-
-
21
-
-
26
-
-
ns
tH
4.5
0
-
-
0
-
-
0
-
-
ns
Switching Specifications CL = 50pF, Input tr, tf = 6ns
25oC PARAMETER HC TYPES Propagation Delay D to Q tPHL CL = 50pF 2 4.5 CL = 15pF CL = 50pF LE to Q tPHL CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF 5 6 15 14 185 37 31 170 34 29 230 46 39 215 43 37 280 56 48 255 51 43 ns ns ns ns ns ns ns ns SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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