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Part: CD74HC273M
Category:
Logic
-> Flip-Flops
-> D-Type Flip-Flops
Description: ti CD74HC273, High Speed CMOS Logic Octal D-type Flip-flops With Reset
Company: Texas Instruments, Inc.
Datasheet: Download CD74HC273M datasheet File size : 173 kB
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Datasheet text preview:
Data sheet acquired from Harris Semiconductor SCHS174B
CD54HC273, CD74HC273, CD54HCT273, CD74HCT273
High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset
Description
The 'HC273 and 'HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with silicon-gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits. Information at the D inputis transferred to the Q outputs on the positive-going edge of the clock pulse. All eight flip-flops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a low voltage level independent of the clock. All eight Q outputs are reset to a logic 0.
February 1998 - Revised May 2003
Features
· Common Clock and Asynchronous Master Reset
[ /Title (CD74 HC273 , CD74 HCT27 3) /Subject (High Speed CMOS Logic Octal DType Flip-
· Positive Edge Triggering · Buffered Inputs · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC273F3A CD74HC273E CD74HC273M CD74HC273M96 CD54HCT273F3A CD74HCT273E CD74HCT273M CD74HCT273M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 20 Ld CERDIP 20 Ld PDIP 20 Ld SOIC 20 Ld SOIC 20 Ld CERDIP 20 Ld PDIP 20 Ld SOIC 20 Ld SOIC
NOTE: When ordering, use the entire par t number. The suffix 96 denotes tape and reel.
Pinout
CD54HC273, CD54HCT273 (CERDIP) CD74HC273, CD74HCT273 (PDIP, SOIC) TOP VIEW
MR 1 Q0 2 D0 3 D1 4 Q1 5 Q2 6 D2 7 D3 8 Q3 9 GND 10 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
1
CD54/74HC273, CD54/74HCT273 Functional Diagram
CLOCK CP D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 DATA OUTPUTS
RESET MR
TRUTH TABLE INPUTS RESET (MR) L H H H CLOCK CP X L DATA Dn X H L X OUTPUT Q L H L Q0
H = High Voltage Level, L = Low Voltage Level, X = Don't Care, = Transition from Low to High Level, Q0 = Level Before the Indicated Steady-State Input Conditions Were Established.
2
CD54/74HC273, CD54/74HCT273
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1) JC (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 160 V V V V V V V V V V V V V V V V µA µA SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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CD54/74HC273, CD54/74HCT273
DC Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 2) VCC to GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
-
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
HCT Input Loading Table
INPUT MR Data CP UNIT LOADS 1.5 0.4 1.5
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC.
Prerequisite For Switching Specifications
PARAMETER HC TYPES Maximum Clock Frequency (Figure 1) fMAX 2 4.5 6 MR Pulse Width (Figure 1) tW 2 4.5 6 6 30 35 60 12 10 5 25 29 75 15 13 4 20 23 90 18 15 MHz MHz MHz ns ns ns SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
4
CD54/74HC273, CD54/74HCT273
Prerequisite For Switching Specifications (Continued)
PARAMETER Clock Pulse Width (Figure 1) SYMBOL tW TEST CONDITIONS VCC (V) 2 4.5 6 Set-up Time Data to Clock (Figure 5) tSU 2 4.5 6 Hold Time, Data to Clock (Figure 5) tH 2 4.5 6 Removal Time, MR to Clock tREM 2 4.5 6 HCT TYPES Maximum Clock Frequency (Figure 2) MR Pulse Width (Figure 2) Clock Pulse Width (Figure 2) Set-up Time Data to Clock (Figure 6) Hold Time, Data to Clock (Figure 6) Removal Time, MR to Clock fMAX tw tw tSU tH tREM 4.5 4.5 4.5 4.5 4.5 4.5 25 12 20 12 3 10 20 15 25 15 3 13 16 18 30 18 3 15 MHz ns ns ns ns ns 25oC MIN 80 16 14 60 12 10 3 3 3 50 10 9 TYP MAX -40oC TO 85oC -55oC TO 125oC MIN 100 20 17 75 15 13 3 3 3 65 13 11 MAX MIN 120 24 20 70 18 15 3 3 3 75 15 13 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns
Switching Specifications Input tr, tf = 6ns
25oC VCC (V) TYP MAX -40oC TO 85oC MAX -55oC TO 125oC MAX UNITS
PARAMETER HC TYPES Propagation Delay, Clock to Output (Figure 3)
SYMBOL
TEST CONDITIONS
tPLH, tPHL
CL = 50pF
2 4.5 6
12 60
150 30 26 150 30 26 75 15 13 10 -
190 38 30 190 38 30 95 19 16 10 -
225 45 38 225 45 38 110 22 19 10 -
ns ns ns ns ns ns ns ns ns ns pF MHz
CL = 15pF Propagation Delay, MR to Output (Figure 3) tPHL CL = 50pF
5 2 4.5 6
Output Transition Time (Figure 3)
tTLH, tTHL
CL = 50pF
2 4.5 6
Input Capacitance Maximum Clock Frequency
CI fMAX
CL = 15pF
5
5
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