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Part: CD74HC74E
Category:
Logic
-> Flip-Flops
-> D-Type Flip-Flops
Description: ti CD74HC74, High Speed CMOS Logic Dual Positive-edge-triggered D-type Flip-flops With Set And Reset
Company: Texas Instruments, Inc.
Datasheet: Download CD74HC74E datasheet File size : 251 kB
Request For quote: Find where to buy CD74HC74E
Datasheet text preview:
CD54HC74, CD74HC74, CD54HCT74, CD74HCT74
Data sheet acquired from Harris Semiconductor SCHS124D
January 1998 - Revised September 2003
Dual D Flip-Flop with Set and Reset Positive-Edge Trigger
Description
The 'HC74 and 'HCT74 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL par ts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. This flip-flop has independent DATA, SET, RESET and CLOCK inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positive-going transition of the clock pulse. SET and RESET are independent of the clock and are accomplished by a low level at the appropriate input. The HCT logic family is functionally as well as pin compatible with the standard LS logic family.
Features [ /Title (CD54H C74, CD74H C74, CD74H CT74) /Subject (Dual D FlipFlop with Set
· Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times · Asynchronous Set and Reset · Complementary Outputs · Buffered Inputs · Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC74F3A CD54HCT74F3A CD74HC74E CD74HC74M CD74HC74MT CD74HC74M96 CD74HCT74E CD74HCT74M CD74HCT74MT CD74HCT74M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC
NOTE: When ordering, use the entire par t number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
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CD54HC74, CD74HC74, CD54HCT74, CD74HCT74 Pinout
CD54HC74, CD54HCT74 (CERDIP) CD74HC74, CD74HCT74 (PDIP, SOIC) TOP VIEW
1R 1 1D 2 1CP 3 1S 4 1Q 5 1Q 6 GND 7 14 VCC 13 2R 12 2D 11 2CP 10 2S 9 2Q 8 2Q
Functional Diagram
1 RESET 2 DATA 3 CLOCK 4 SET RESET 13 R D 11 CLOCK 10 F/F 2 CP S SET 8 Q GND = PIN 7 VCC = PIN 14 D F/F 1 CP S 6 Q R 5 Q
12 DATA
9 Q
TRUTH TABLE INPUTS SET L H L H H H RESET H L L H H H CP X X X D X X X H L X Q H L H (Note 1) H L Q0 OUTPUTS Q L H H (Note 1) L H Q0
L
H= High Level (Steady State) L= Low Level (Steady State) X= Don't Care = Low-to-High Transition Q0 = the level of Q before the indicated input conditions were established. NOTE: 1. This configuration is nonstable, that is, it will not persist when set and reset inputs return to their inactive (high) level.
2
CD54HC74, CD74HC74, CD54HCT74, CD74HCT74
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 2 4.5 6 -4 -5.2 0.02 4.5 6 2 4.5 6 4 5.2 4.5 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 V V V V V V V V V V V V V V V V V V µA SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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CD54HC74, CD74HC74, CD54HCT74, CD74HCT74
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER Quiescent Device Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II VCC and GND VCC or GND VCC - 2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL ICC VI (V) VCC or GND IO (mA) VCC (V) 0 6 MIN 25oC TYP MAX 4 -40oC TO 85oC MIN MAX 40 -55oC TO 125oC MIN MAX 80 UNITS µA
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02 4
4.5 4.5
-
-
0.1 0.26
-
0.1 0.33
-
0.1 0.4
V V
-
5.5
-
±0.1
-
±1
-
±1
µA
ICC ICC (Note 3)
0 -
5.5 4.5 to 5.5
-
100
4 360
-
40 450
-
80 490
µA µA
HCT Input Loading Table
INPUT D R CP S UNIT LOADS 0.5 0.5 0.7 0.75
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC.
Prerequisite For Switching Specifications
PARAMETER HC TYPES Data to CP Setup Time (Figure 5) tSU 2 4.5 6 60 12 10 75 15 13 90 18 15 ns ns ns SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
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CD54HC74, CD74HC74, CD54HCT74, CD74HCT74
Prerequisite For Switching Specifications
PARAMETER Hold Time (Figure 5) SYMBOL tH (Continued) VCC (V) 2 4.5 6 Removal Time R, S, to CP (Figure 5) tREM 2 4.5 6 Pulse Width R, S (Figure 1) tW 2 4.5 6 Pulse Width CP (Figure 1) tW 2 4.5 6 CP Frequency fMAX 2 4.5 6 HCT TYPES Data to CP Setup Time (Figure 6) Hold Time (Figure 6) Removal Time R, S, to CP (Figure 6) Pulse Width R, S (Figure 2) Pulse Width CP (Figure 2) CP Frequency tSU tH tREM tW tW fMAX 4.5 4.5 4.5 4.5 4.5 4.5 12 3 6 16 18 25 15 3 8 20 23 20 18 3 9 24 27 16 ns ns ns ns ns MHz 25oC MIN 3 3 3 30 6 5 80 16 14 80 16 14 6 30 35 TYP MAX -40oC TO 85oC -55oC TO 125oC MIN 3 3 3 40 8 7 100 20 17 100 20 17 5 25 29 MAX MIN 3 3 3 45 9 8 120 24 20 120 24 20 4 20 23 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz
TEST CONDITIONS -
Switching Specifications Input tr, tf = 6ns
PARAMETER HC TYPES Propagation Delay, CP to Q, Q (Figure 3) tPLH, tPHL CL = 50pF CL = 50pF CL = 15pF CL = 50pF Propagation Delay, R, S to Q, Q (Figure 3) tPLH, tPHL CL = 50pF CL = 50pF CL = 15pF CL = 50pF Transition Time (Figure 3) tTLH, tTHL CL = 50pF CL = 50pF CL = 50pF Input Capacitance CI 2 4.5 5 6 2 4.5 5 6 2 4.5 6 14 17 175 35 30 200 40 34 75 15 13 10 220 44 37 250 50 43 95 19 16 10 265 53 45 300 60 51 110 22 19 10 ns ns ns ns ns ns ns ns ns ns ns pF SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
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