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Part: CD74HC85MT
Category:
Logic
-> Comparators
-> Magnitude Comparators
Description: ti CD74HC85, High Speed CMOS Logic 4-Bit Magnitude Comparator
Company: Texas Instruments, Inc.
Datasheet: Download CD74HC85MT datasheet File size : 251 kB
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Datasheet text preview:
CD54HC85, CD74HC85, CD54HCT85, CD74HCT85
Data sheet acquired from Harris Semiconductor SCHS136E
August 1997 - Revised October 2003
High-Speed CMOS Logic 4-Bit Magnitude Comparator
Description
The 'HC85 and 'HCT85 are high speed magnitude comparators that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits. These 4-bit devices compare two binar y, BCD, or other monotonic codes and present the three possible magnitude results at the outputs (A > B, A < B, and A = B). The 4-bit input words are weighted (A0 to A3 and B0 to B3), where A3 and B3 are the most significant bits. The devices are expandable without external gating, in both serial and parallel fashion. The upper par t of the truth table indicates operation using a single device or devices in a serially expanded application. The parallel expansion scheme is described by the last three entries in the truth table.
Features
· Buffered Inputs and Outputs
[ /Title (CD74 HC85, CD74 HCT85 ) /Subject (High Speed CMOS Logic 4-Bit Magnitude Compara-
· Typical Propagation Delay: 13ns (Data to Output at VCC = 5V, CL = 15pF, TA = 25oC · Serial or Parallel Expansion Without External Gating · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC85F3A CD54HCT85F3A CD74HC85E CD74HC85M TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld SOP 16 Ld TSSOP 16 Ld TSSOP 16 Ld TSSOP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC
Pinout
CD54HC85, CD54HCT85 (CERDIP) CD74HC85 (PDIP, SOIC, SOP, TSSOP) CD74HCT85 (PDIP, SOIC) TOP VIEW
B3 1 (A B) IN 4 (A > B) OUT 5 (A = B) OUT 6 (A < B) OUT 7 GND 8 16 VCC 15 A3 14 B2 13 A2 12 A1 11 B1 10 A0 9 B0
CD74HC85MT CD74HC85M96 CD74HC85NSR CD74HC85PW CD74HC85PWR CD74HC85PWT CD74HCT85E CD74HCT85M CD74HCT85MT CD74HCT85M96
NOTE: When ordering, use the entire par t number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
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CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 PFunctional Diagram
A3 A2 A1 A0 (A B) IN B3 B2 11 B1 9 B0 15 13 12 10 2 3 4 1 14 7 6 5 (A B) OUT
TRUTH TABLE COMPARING INPUTS A3, B3 A2, B2 A1, B1 A0, B0 CASCADING INPUTS A>B AB OUTPUTS A
SINGLE DEVICE OR SERIES CASCADING A3 > B3 A3 B2 A2 B1 A1 B0 A0 < B0 A0 = B0 A0 = B0 A0 = B0 X X X X X X X X H L L X X X X X X X X L H L X X X X X X X X L L H H L H L H L H L H L L L H L H L H L H L H L L L L L L L L L L L H
PARALLEL CASCADING A3 = B3 A3 = B3 A3 = B3 A2 = B2 A2 = B2 A2 = B2S A1 = B1 A1 = B1 A1 = B1 A0 = B0 A0 = B0 A0 = B0 X H L X H L H L L L L H L L H H L L
H = High Voltage Level, L = Low Voltage, Level, X = Don't Care
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CD54HC85, CD74HC85, CD54HCT85, CD74HCT85
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Package Thermal Impedance, JA (see Note 1): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 2 4.5 6 4.5 6 2 4.5 6 4.5 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 V V V V V V V V V V V V V V V V SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
5.2 0
6 6 6
-
-
0.26 ±0.1 8
-
0.33 ±1 80
-
0.4 ±1 160
V µA µA
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CD54HC85, CD74HC85, CD54HCT85, CD74HCT85
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 2) VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
HCT Input Loading Table
INPUT A0-A3, B0-B3 and (A = B) IN (A > B) IN, (A < B) IN UNIT LOADS 1.5 1
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g. 360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
TEST CONDITIONS 25oC VCC (V) 2 4.5 CL = 15pF CL = 50pF An, Bn to (A = B) OUT tPLH, tPHL CL = 50pF CL = 15pF CL = 50pF 5 6 2 4.5 5 6 MIN TYP 16 14 MAX 195 39 33 175 35 30 -40oC TO 85oC MIN MAX 245 47 42 240 44 37 -55oC TO 125oC MIN MAX 295 59 50 265 53 45 UNITS ns ns ns ns ns ns ns ns
PARAMETER HC TYPES Propagation Delay, An, Bn to (A > B) OUT, (A < B) OUT
SYMBOL
tPLH, tPHL CL = 50pF
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CD54HC85, CD74HC85, CD54HCT85, CD74HCT85
Switching Specifications Input tr, tf = 6ns (Continued)
TEST CONDITIONS 25oC VCC (V) 2 4.5 5 6 2 4.5 CL = 15pF CL = 50pF Power Dissipation Capacitance (Notes 3, 4) Output Transition Times (Figure 1) CPD 5 6 5 2 4.5 6 Input Capacitance HCT TYPES Propagation Delay, An, Bn to (A > B) OUT, (A < B) OUT An, Bn to (A = B) OUT CIN 4.5 5 4.5 5 4.5 5 4.5 5 4.5 5 MIN TYP 11 9 24 15 17 12 13 26 MAX 140 28 24 120 24 20 75 15 13 10 37 40 30 31 15 10 -40oC TO 85oC MIN MAX 175 35 30 150 30 26 95 19 16 10 46 50 38 39 19 10 -55oC TO 125oC MIN MAX 210 42 36 180 36 31 110 22 19 10 56 60 45 47 22 10 UNITS ns ns ns ns ns ns ns ns pF ns ns ns pF ns ns ns ns ns ns ns ns ns pF pF
PARAMETER
SYMBOL
(A > B) IN, (A B) OUT, (A B) IN to (A = B) OUT tPLH, tPHL CL = 50pF
tTLH, tTHL CL = 50pF
tPLH, tPHL CL = 50pF CL = 15pF tPLH, tPHL CL = 50pF CL = 15pF
(A > B) IN, (A B) OUT, (A B) IN to (A = B) OUT Output Transition Times (Figure 1) Power Dissipation Capacitance (Notes 3, 4) Input Capacitance NOTES: tPLH, tPHL CL = 50pF CL = 15pF tTLH, tTHL CL = 50pF CPD CIN -
3. CPD is used to determine the dynamic power consumption, per gate/package. 4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuits and Waveforms
tr = 6ns INPUT 90% 50% 10% tTLH 90% 50% 10% tPHL tPLH tf = 6ns VCC INPUT GND tTHL tr = 6ns 2.7V 1.3V 0.3V tTLH 90% INVERTING OUTPUT tPHL tPLH 1.3V 10% tf = 6ns 3V
GND
tTHL
INVERTING OUTPUT
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
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