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Part: CD74HC93E
Category:
Logic
-> Counters
-> Binary Counters
Description: ti CD74HC93, High Speed CMOS Logic 4-Bit Binary Ripple Counter
Company: Texas Instruments, Inc.
Datasheet: Download CD74HC93E datasheet File size : 251 kB
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Datasheet text preview:
CD74HC93, CD74HCT93
Data sheet acquired from Harris Semiconductor SCHS138C
August 1997 - Revised September 2003
High-Speed CMOS Logic 4-Bit Binary Ripple Counter
Description
The CD74HC93 and CD74HCT93 are high-speed silicon-gate CMOS devices and are pin-compatible with low power Schottky TTL (LSTTL). These 4-bit binary ripple counters consist of four master-slave flip-flops internally connected to provide a divide-by-two section and a divide- by-eight section. Each section has a separate clock input (CP0 and CP1) to initiate state changes of the counter on the HIGH to LOW clock transition. State changes of the Qn outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. A gated AND asynchronous master reset (MR1 and MR2 is provided which overrides both clocks and resets (clears) all flip-flops. Because the output from the divide by two section is not internally connected to the succeeding stages, the device may be operated in various counting modes. In a 4-bit ripple counter the output Q0 must be connected externally to input CP1. The input count pulses are applied to clock input CP0. Simultaneous frequency divisions of 2, 4, 8, and 16 are performed at the Q0, Q1, Q2, and Q3 outputs as shown in the function table. As a 3-bit ripple counter the input count pulses are applied to input CP1. Simultaneous frequency divisions of 2, 4, and 8 are available at the Q1, Q2, Q3 outputs. Independent use of the first flipflop is available if the reset function coincides with the reset of the 3-bit ripple-through counter.
Features
· Can Be Configured to Divide By 2, 8, and 16
[ /Title (CD74 HC93, CD74 HCT93 ) /Subject (High Speed CMOS Logic 4-Bit Binary Ripple Counte r)
· Asynchronous Master Reset · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Pinout
CD74HC93 (PDIP, SOIC) CD74HCT93 (PDIP) TOP VIEW
CP1 1 MR1 2 MR2 3 NC 4 VCC 5 NC 6 NC 7 14 CPO 13 NC 12 Q0 11 Q3 10 GND 9 Q1 8 Q2
Ordering Information
PART NUMBER CD74HC93E CD74HC93M CD74HC93MT CD74HC93M96 CD74HCT93E TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld PDIP
NOTE: When ordering, use the entire par t number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
1
CD74HC93, CD74HCT93
TRUTH TABLE OUTPUTS COUNT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Q0 L H L H L H L H L H L H L H L H Q1 L L H H L L H H L L H H L L H H Q2 L L L L H H H H L L L L H H H H Q3 L L L L L L L L H H H H H H H H
H = High Voltage Level, L = Low Voltage Level
MODE SELECTION RESET OUTPUTS MR1 H L H L MR2 H H L L Q0 L Count Q1 L Count OUTPUTS Q2 L Count Q3 L Count
H = High Voltage Level, L = Low Voltage Level
2
CD74HC93, CD74HCT93
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 86 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 160 V V V V V V V V V V V V V V V V µA µA SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
3
CD74HC93, CD74HCT93
DC Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 2) VCC to GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
-
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
HCT Input Loading Table
INPUT CP0, CP1 MR1, MR2 UNIT LOADS 0.6 0.4
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC.
Prerequisite For Switching Specifications
PARAMETER HC TYPES Maximum Clock Frequency fMAX 2 4.5 6 Clock Pulse Width CP0, CP1 tw 2 4.5 6 6 30 35 80 16 14 5 24 28 100 20 17 4 20 24 120 24 20 MHz MHz MHz ns ns ns SYMBOL TEST CONDITIONS VCC (V) 25oC MIN MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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CD74HC93, CD74HCT93
Prerequisite For Switching Specifications
PARAMETER Reset Pulse Width SYMBOL tW (Continued) 25oC MIN 80 16 14 50 10 9 MAX -40oC TO 85oC MIN 100 20 17 65 13 11 MAX -55oC TO 125oC MIN 120 24 20 75 15 13 MAX UNITS ns ns ns ns ns ns
TEST CONDITIONS VCC (V) 2 4.5 6
Reset Removal Time
tREM
2 4.5 6
HCT TYPES Maximum Clock Frequency Clock Pulse Width CP0, CP1 Reset Pulse Width Reset Removal Time fMAX tW tW tREM 4.5 4.5 4.5 4.5 30 16 16 10 24 20 20 13 20 24 24 15 mHz ns ns ns
Switching Specifications Input tr, tf = 6ns
TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
PARAMETER HC TYPES Propagation Delay Time CP0 to Q0
SYMBOL
tPLH, tPHL
CL = 50pF CL = 50pF CL = 15pF CL = 50pF
2 4.5 5 6 2 4.5 6 2 4.5 6 2 4.5 5 6 2 4.5 5 6 2 4.5 6
-
10 -
125 25
-
155 31 26 170 34 29 230 46 39 305 61 52 195 39
-
190 38 32 205 41 35 280 56 48 370 74 63 235 47 40 110 22 19 10 19
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF
21 135 27 23 185 37 31 245 49
-
CP1 to Q1
tPLH, tPHL
CL = 50pF CL = 50pF CL = 50pF
CP1 to Q2
tPLH, tPHL
CL = 50pF CL = 50pF CL = 50pF
CP1 to Q3
tPLH, tPHL
CL = 50pF CL = 50pF CL = 15pF CL = 50pF
21 -
42 155 31
MR1, MR2 to Qn
tPLH, tPHL
CL = 50pF CL = 50pF CL = 15pF CL = 50pF
13 26 25 75 15 13 10 -
-
33 95 19 16 10 10
-
Output Transition Time
tTLH, tTHL
CL = 50pF
Input Capacitance Power Dissipation Capacitance
CIN CPD
CL = 50pF -
-
5
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