Part  CD74HCT390 
Category  Semiconductors => Logic => Specialty Logic => Counter/Arithmetic/Parity Function 
Part family  CD74HCT390 High Speed CMOS Logic Dual Decade Ripple Counter 
Title  CMOS/BiCMOS>HC/HCT Family 
Description  High Speed CMOS Logic Dual Decade Ripple Counter 16PDIP 55 to 125 
Company  Texas Instruments, Inc. 
Status  ACTIVE 
ROHS  Compliant 
Sample  No 
Datasheet  Download CD74HCT390 datasheet

Cross ref.  Similar parts: SN74LS390D, SN74LS390DR2, SN74LS390J, SN74LS390JD, SN74LS390JDS, SN74LS390JS, SN74LS390N, SN74LS390ND, SN74LS390NDS, SN74LS390NS 
Quote 
Specifications  
tpd @ Nom Voltage(Max)(ns)  69 
ICC @ Nom Voltage(Max)(mA)  0.08 
Rating  Catalog 
Schmitt Trigger  No 
Output Type  CMOS 
Voltage(Nom)(V)  5 
Bits(#)  4 
F @ Nom Voltage(Max)(Mhz)  25 
Operating Temperature Range(C)  55 to 125 
Input Type  TTL 
Function  Counter 
VCC(Max)(V)  5.5 
Type  Decade 
Technology Family  HCT 
Package Group  PDIP,SOIC 
Output Drive (IOL/IOH)(Max)(mA)  4/4 
Approx. Price (US$)  0.19  1ku 
VCC(Min)(V)  4.5 
Pin nb  Package type  Ind std  JEDEC code  Package qty  Carrier  Device mark  Width (mm)  Length (mm)  Thick (mm)  Pitch (mm) 

16  N  PDIP  RPDIPT  25  TUBE  CD74HCT390E  6.35  19.3  3.9  2.54 
Features, Applications 
Data sheet acquired from Harris Semiconductor SCHS185A High Speed CMOS Logic Dual Decade Ripple Counter Description The CD74HC390 and 'HCT390 dual 4bit decade ripple counters are highspeed silicongate CMOS devices and are pin compatible with lowpower Schottky TTL (LSTTL). These devices are divided into four separately clocked sections. The counters have two divideby2 sections and two divideby5 sections. These sections are normally used in a BCD decade or biquinary configuration, since they share a common master reset (nMR). If the two master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are possible within one package. The separate clock inputs (nCP0 and nCP1) of each section allow ripple counter or frequency division applications or 100. Each section is triggered by the HightoLow transition of the input pulses (nCP0 and nCP1). For BCD decade operation, the nQ0 output is connected to the nCP1 input of the divideby5 section. For biquinary decade operation, the nO3 output is connected to the nCP0 input and nQ0 becomes the decade output. The master reset inputs (1MR and 2MR) are activeHigh asynchronous inputs to each decade counter which operates on the portion of the counter identified by the "1" and "2" prefixes in the pin configuration. A High level on the nMR input overrides the clock and sets the four outputs Low. FeaturesTwo BCD Decade or BiQuinary Counters One Package Can Be Configured or 100 Two Master Reset Inputs to Clear Each Decade Counter Individually Fanout (Over Temperature Range)  Standard Outputs. 10 LSTTL Loads  Bus Driver Outputs. 15 LSTTL Loads Wide Operating Temperature Range. to 125oC Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types to 6V Operation  High Noise Immunity: NIL = 30%, NIH 30% of VCC at VCC = 5V HCT Types to 5.5V Operation  Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)  CMOS Input Compatibility, 1ľA at VOL, VOH PART NUMBER TEMP. RANGE (oC) to 125 PACKAGE 16 Ld PDIP 16 Ld SOIC 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright TRUTH TABLE INPUTS L H ACTION No Change Count All Qs LowNOTE: H = High Voltage Level, L = Low Voltage Level, X = Don't Care, = Transition from Low to High Level, = Transition from High to Low. NOTE: Output nQ0 connected to nCP1 with counter input on nCP0.NOTE: Output nQ3 connected to nCP0 with counter input on nCP1. 
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