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Part: CD74HCT4075E
Category:
Logic
-> Gates
-> OR Gates
Description: ti CD74HCT4075, High Speed CMOS Logic Triple 3-Input OR GATEs
Company: Texas Instruments, Inc.
Datasheet: Download CD74HCT4075E datasheet File size : 173 kB
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Datasheet text preview:
CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075
Data sheet acquired from Harris Semiconductor SCHS210F
August 1997 - Revised August 2003
High-Speed CMOS Logic Triple 3-Input OR Gate
Description
The 'HC4075 and 'HCT4075 logic gates utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally pin compatible with the standard LS logic family.
Features
· Buffered Inputs
[ /Title (CD74H C4075, CD74H CT4075) /Subject (High Speed CMOS Logic Triple 3Input
· Typical Propagation Delay: 8ns at VCC = 5V, CL = 15pF, TA = 25oC · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC4075F3A CD54HCT4075F3A CD74HC4075E CD74HC4075M CD74HC4075MT CD74HC4075M96 CD74HC4075NSR CD74HC4075PW CD74HC4075PWR CD74HC4075PWT CD74HCT4075E TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld SOP 14 Ld TSSOP 14 Ld TSSOP 14 Ld TSSOP 14 Ld PDIP
NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250.
Pinout
CD54HC4075, CD54HCT4075 (CERDIP) CD74HC4075 (PDIP, SOIC, SOP, TSSOP) CD74HCT4075 (PDIP) TOP VIEW
2A 1 2B 2 1A 3 1B 4 1C 5 1Y 6 GND 7 14 VCC 13 3C 12 3B 11 3A 10 3Y 9 2Y 8 2C
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
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CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 Functional Diagram
1A 1B 1C 2A 2B 2C 3A 3B 3C 13 3 4 5 1 2 8 11 12 10 3Y GND = 7 VCC = 14 9 2Y 6 1Y
TRUTH TABLE INPUTS nA L H X X nB L X H X nC L X X H OUTPUT nY L H H H
H = High Voltage Level, L = Low Voltage Level, X = Irrelevant
Logic Diagram
nA
nB
nY
nC
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CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Package Thermal Impedance, JA (see Note 1): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80oC/W M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76oC/W PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 113oC/W Maximum Junction Temperature (Hermetic Package or Die) . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 2 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 20 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 40 V V V V V V V V V V V V V V V V µA µA SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
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CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 2) VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
100
±0.1 2 360
-
±1 20 450
-
±1 40 490
µA µA µA
HCT Input Loading Table
INPUT All UNIT LOADS 1.6
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g. 360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
TEST CONDITIONS 25oC VCC (V) MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
PARAMETER HC TYPES Propagation Delay, Input to Output (Figure 1)
SYMBOL
tPLH, tPHL
CL = 50pF
2 4.5 6
-
8 -
100 20 17 75 15 13 10
-
125 25 21 95 19 16 10
-
150 30 26 110 22 19 10
ns ns ns ns ns ns ns pF
CL = 15pF Transition Times (Figure 1) tTLH, tTHL CL = 50pF
5 2 4.5 6
Input Capacitance
CIN
-
-
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CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075
Switching Specifications Input tr, tf = 6ns (Continued)
TEST CONDITIONS 25oC VCC (V) 5 MIN TYP 26 MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS pF
PARAMETER Power Dissipation Capacitance (Notes 3, 4) HCT TYPES Propagation Delay, Input to Output (Figure 2) Transition Times (Figure 2) Input Capacitance Power Dissipation Capacitance (Notes 3, 4) NOTES:
SYMBOL CPD
tPLH, tPHL
CL = 50pF CL = 15pF
4.5 5 4.5 5
-
9 28
24 15 10 -
-
30 19 10 -
-
36 22 10 -
ns ns ns pF pF
tTLH, tTHL CIN CPD
CL = 50pF -
3. CPD is used to determine the dynamic power consumption, per gate. 4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuits and Waveforms
tr = 6ns INPUT 90% 50% 10% tTLH 90% 50% 10% tPHL tPLH tf = 6ns VCC INPUT GND tTHL tr = 6ns 2.7V 1.3V 0.3V tTLH 90% INVERTING OUTPUT tPHL tPLH 1.3V 10% tf = 6ns 3V
GND
tTHL
INVERTING OUTPUT
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
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