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Part: CD74HCT4094M96
Category:
Logic
-> Registers
Description: ti CD74HCT4094, High Speed CMOS Logic 8-Stage Shift-and-store Bus Register With 3-Stage Outputs
Company: Texas Instruments, Inc.
Datasheet: Download CD74HCT4094M96 datasheet File size : 173 kB
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Datasheet text preview:
CD54HC4094, CD74HC4094, CD74HCT4094
Data sheet acquired from Harris Semiconductor SCHS211D
November 1997 - Revised October 2003
High-Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State
Two serial outputs are available for cascading a number of these devices. Data is available at the QS1 serial output terminal on positive clock edges to allow for high-speed operation in cascaded system in which the clock rise time is fast. The same serial information, available at the QS2 terminal on the next negative clock edge, provides a means for cascading these devices when the clock rise time is slow.
Features
· Buffered Inputs
[ /Title (CD74H C4094, CD74H CT4094 ) /Subject (High Speed CMOS Logic 8-
· Separate Serial Outputs Synchronous to Both Positive and Negative Clock Edges For Cascading · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC4094F3A CD74HC4094E CD74HC4094M CD74HC4094MT CD74HC4094M96 CD74HC4094NSR CD74HC4094PW CD74HC4094PWR CD74HC4094PWT CD74HCT4094E CD74HCT4094M CD74HCT4094MT CD74HCT4094M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld SOP 16 Ld TSSOP 16 Ld TSSOP 16 Ld TSSOP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC
Description
The 'HC4094 and CD74HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input to parallel buffered three-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs whenever the Output-Enable signal is high.
NOTE: When ordering, use the entire par t number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250.
Pinout
CD54HC4094 (CERDIP) CD74HC4094 (PDIP, SOIC, SOP, TSSOP) CD74HCT4094 (PDIP, SOIC) TOP VIEW
STROBE 1 DATA 2 CP 3 Q0 4 Q1 5 Q2 6 Q3 7 GND 8 16 VCC 15 OE 14 Q4 13 Q5 12 Q6 11 Q7 10 QS2 9 QS1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
1
CD54HC4094, CD74HC4094, CD74HCT4094 Functional Diagram
2 DATA CP 3 8-STAGE SHIFT REGISTER 9 QS1 10 QS2
1 STROBE
8-BIT STORAGE REGISTER
4 5 6 7 15 OE THREESTATE OUTPUT 14 13 12 11 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 GND = 8 VCC = 16
TRUTH TABLE INPUTS CP OE L L H H H H STR X X L H H H D X X X L H H PARALLEL OUTPUTS Q0 Z Z NC L H NC Qn Z Z NC Qn -1 Qn -1 NC SERIAL OUTPUTS QS1 (NOTE 1) Q'6 NC Q'6 Q'6 Q'6 NC QS2 NC Q7 NC NC NC Q7
H = High Voltage Level, L = Low Voltage Level, X = Don't Care, NC = No charge, Z = High Impedance Off-state, = Transition from Low to High Level, = Transition from High to Low. NOTE: 1. At the positive clock edge the information in the seventh register stage is transferred to the 8th register stage and QS1 output.
2
Logic Diagram
D FFO CP CP FF1 FF2 FF3 FF4 FF5 FF 6 FF7
Q
2
DATA
9 QS1
3
CP CP D L8 Q CP
1
STR
CD54HC4094, CD74HC4094, CD74HCT4094
3
STR STR LO Q L1 L2 L3 L4 OE OE 4 Q0 5 Q1 6 Q2 7 Q3
10 QS2 L5 L6 L7
15
OE
14 Q4
13 Q5
12 Q6
11 Q7
CD54HC4094, CD74HC4094, CD74HCT4094
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Package Thermal Impedance, JA (see Note 2): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W M (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64oC/W PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature (Plastic Package) . . . . . . . . . 150o Maximum Storage Temperature Range . . . . . . . . . . . -65oC to 150o Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . 300o SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 160 V V V V V V V V V V V V V V V V V V µA µA SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
4
CD54HC4094, CD74HC4094, CD74HCT4094
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 3) VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
-
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
HCT Input Loading Table
INPUT D CP, OE STR UNIT LOADS 0.4 1.5 1.0
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC.
Prerequisite for Switching Specifications
25oC CHARACTERISTIC HC TYPES CP Pulse Width tW 2 4.5 6 STR Pulse Width tWH 2 4.5 6 80 16 14 80 16 14 100 20 17 100 20 17 120 24 20 120 24 20 ns ns ns ns ns ns SYMBOL VCC (V) MIN MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
5
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