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Part: CD74HCT42
Category:
Logic
-> Decoder/Demultiplexers
-> CMOS/BiCMOS->HC/HCT Family
Description: High Speed CMOS Logic BCD to Decimal Decoder (1 of 10)
Company: Texas Instruments, Inc.
Datasheet: Download CD74HCT42 datasheet File size : 173 kB
Request For quote: Find where to buy CD74HCT42
Datasheet text preview:
CD54/74HC42, CD74HCT42
Data sheet acquired from Harris Semiconductor SCHS133A
August 1997 - Revised May 2000
High Speed CMOS Logic BCD To Decimal Decoder (1 of 10)
Description
The 'HC42 and CD74HCT42 BCD-to-Decimal Decoders utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL decoders with the low power consumption of standard CMOS integrated circuits. These devices have the capability of driving 10 LSTLL loads and are compatible with the standard LS logic family. One of ten outputs (low on select) is selected in accordance with the BCD input. Non-valid BCD inputs result in none of the outputs being selected (all outputs are high).
Features
· Buffered Inputs and Outputs
[ /Title (CD74H C42, CD74H CT42) /Subject High peed MOS ogic CD To eci-
· Typical Propagation Delay: 12ns at VCC = 5V, CL = 15pF, TA = 25oC · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC42F3A CD74HC42E CD74HC42M CD74HCT42E NOTES: 1. When ordering, use the entire par t number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP
Pinout
CD54HC42 (CERDIP) CD74HC42, CD74HCT42 (PDIP, SOIC) TOP VIEW
Y0 1 Y1 2 Y2 3 Y3 4 Y4 5 Y5 6 Y6 7 GND 8 16 VCC 15 A0 14 A1 13 A2 12 A3 11 Y9 10 Y8 9 Y7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2000 Texas Instruments Incorporated.
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CD54/74HC42, CD74HCT42 Functional Diagram
1 A0 A1 A2 A3 15 14 13 12 2 3 4 5 6 7 9 10 11 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9
TRUTH TABLE INPUTS A3 L L L L L L L L H H H H H H H H A2 L L L L H H H H L L L L H H H H A1 L L H H L L H H L L H H L L H H A0 L H L H L H L H L H L H L H L H Y0 L H H H H H H H H H H H H H H H Y1 H L H H H H H H H H H H H H H H Y2 H H L H H H H H H H H H H H H H Y3 H H H L H H H H H H H H H H H H OUTPUTS Y4 H H H H L H H H H H H H H H H H Y5 H H H H H L H H H H H H H H H H Y6 H H H H H H L H H H H H H H H H Y7 H H H H H H H L H H H H H H H H Y8 H H H H H H H H L H H H H H H H Y9 H H H H H H H H H L H H H H H H
NOTE: H = High Voltage Level, L = Low Voltage Level
2
CD54/74HC42, CD74HCT42
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 3) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 160 V V V V V V V V V V V V V V V V V V µA µA SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
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CD54/74HC42, CD74HCT42
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II ICC ICC VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT All UNIT LOADS 1
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g. 360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
TEST CONDITIONS 25oC VCC (V) MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
PARAMETER HC TYPES Propagation Delay, Input to Y (Figure 1)
SYMBOL
tPLH, tPHL
CL = 50pF
2 4.5 6
-
12 -
150 30 26 75 15 13 10
-
190 38 33 95 19 16 10
-
225 45 38 110 22 19 10
ns ns ns ns ns ns ns pF
Any Input to Y Output Transition Time (Figure 1)
tPLH, tPHL tTLH, tTHL
CL = 15pF CL = 50pF
5 2 4.5 6
Input Capacitance
CIN
-
-
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CD54/74HC42, CD74HCT42
Switching Specifications Input tr, tf = 6ns (Continued)
TEST CONDITIONS 25oC VCC (V) 5 MIN TYP 65 MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS pF
PARAMETER Power Dissipation Capacitance (Notes 4, 5) HCT TYPES Propagation Delay, Input to Y (Figure 2) Any Input to Y Output Transition Time (Figure 2) Input Capacitance Power Dissipation Capacitance (Notes 4, 5) NOTES:
SYMBOL CPD
tPLH, tPHL tPLH, tPHL tTLH, tTHL CIN CPD
CL = 50pF CL = 15pF CL = 50pF -
4.5 5 4.5 5
-
14 70
35 15 10 -
-
44 19 10 -
-
53 22 10 -
ns ns ns pF pF
4. CPD is used to determine the dynamic power consumption, per package. 5. PD = VCC2 fi (CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuits and Waveforms
tr = 6ns INPUT 90% 50% 10% tTLH 90% 50% 10% tPHL tPLH tf = 6ns VCC INPUT GND tTHL tr = 6ns 2.7V 1.3V 0.3V tTLH 90% INVERTING OUTPUT tPHL tPLH 1.3V 10% tf = 6ns 3V
GND
tTHL
INVERTING OUTPUT
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
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