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Part: CD74HCT4520M
Category:
Logic
-> Counters
-> Binary Counters
Description: ti CD74HCT4520, High Speed CMOS Logic Dual Binary Up-counters
Company: Texas Instruments, Inc.
Datasheet: Download CD74HCT4520M datasheet File size : 188 kB
Request For quote: Find where to buy CD74HCT4520M
Datasheet text preview:
CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520
Data sheet acquired from Harris Semiconductor SCHS216D
November 1997 - Revised October 2003
High-Speed CMOS Logic Dual Synchronous Counters
having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or the negativegoing transition of CLOCK. The counters are cleared by high levels on the MASTER RESET lines. The counter can be cascaded in the ripple mode by connecting Q3 to the ENABLE input of the subsequent counter while the CLOCK input of the latter is held low.
Features
· Positive or Negative Edge Triggering
[ /Title (CD74 HC451 8, CD74 HC452 0, CD74 HCT45 20) /Subject
· Synchronous Internal Carry Propagation · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC4520F3A CD74HC4518E CD74HC4520E CD74HC4520M CD74HC4520MT CD74HC4520M96 CD74HCT4520E CD74HCT4520M CD74HCT4520MT CD74HCT4520M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld PDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC
Description
The CD74HC4518 is a dual BCD up-counter. The 'HC4520 and CD74HCT4520 are dual binar y up-counters. Each device consists of two independent internally synchronous 4-stage counters. The counter stages are D-type flip-flops
NOTE: When ordering, use the entire par t number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250.
Pinout
CD54HC4520 (CERDIP) CD74HC4518 (PDIP) CD74HC4520, CD74HCT4520, (PDIP, SOIC) TOP VIEW
1CP 1 1E 2 1Q0 3 1Q1 4 1Q2 5 1Q3 6 1MR 7 GND 8
16 VCC 15 2MR 14 2Q3 13 2Q2 12 2Q1 11 2Q0 10 2E 9 2CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
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CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520 Functional Diagram
1CP 1
÷10/÷16
CL R
3 1Q0 4 1Q1 5 1Q2 6 1Q3
1E
2
1MR
7
2CP
9
÷10/÷16
CL R
11 2Q0 12 2Q1 13 2Q2 14 2Q3
2E
10
2MR
15
GND = 8 VCC = 16
TRUTH TABLE CP L X H X H L X = High State. = Low State. = High-to-Low Transition. = Low-to-High Transition. = Don't Care. E H X L X MR L L L L L L H OUTPUT STATE Increment Counter Increment Counter No Change No Change No Change No Change Q0 thru Q3 = L
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CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 160 V V V V V V V V V V V V V V V V V V µA µA SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 2) VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
-
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
HCT Input Loading Table
INPUT MR CP ENABLE UNIT LOADS 1.2 0.25 0.5
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC.
Prerequisite for Switching Specifications
25oC PARAMETER HC TYPES Maximum Clock Frequency fMAX 2 4.5 6 CP Pulse Width tW 2 4.5 6 MR Pulse Width tW 2 4.5 6 6 30 35 80 16 14 100 20 17 5 24 28 100 20 17 125 25 21 4 20 24 120 24 20 150 30 26 MHz MHz MHz ns ns ns ns ns ns SYMBOL VCC (V) MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520
Prerequisite for Switching Specifications
PARAMETER Set-up Time, Enable to CP SYMBOL tSU VCC (V) 2 4.5 6 Removal Time, MR to CP tREM 2 4.5 6 Set-up Time, CP to Enable tSU 2 4.5 6 Removal Time, MR to Enable tREM 2 4.5 6 HCT TYPES Maximum Clock Frequency Clock Pulse Width MR Pulse Width Set-up Time, Enable to CP Removal Time, MR tp Enable fMAX tW tW tSU tREM 4.5 4.5 4.5 4.5 4.5 25 20 20 16 0 20 25 25 20 0 17 30 30 24 0 MHz ns ns ns ns (Continued) 25oC MIN 80 16 14 0 0 0 80 16 14 0 0 0 TYP MAX -40oC TO 85oC MIN 100 20 17 0 0 0 100 20 17 0 0 0 MAX -55oC TO 125oC MIN 120 24 20 0 0 0 120 24 20 0 0 0 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns
Switching Specifications Input tr, tf = 6ns
TEST SYMBOL CONDITIONS tPLH, tPHL CL = 50pF CL = 50pF CL = 15pF CL = 50pF Enable to Qn tPLH, tPHL CL = 50pF CL = 50pF CL = 15pF CL = 50pF MR to Qn tPLH, tPHL CL = 50pF CL = 50pF CL = 15pF CL = 50pF Output Transition Time tTHL, tTLH CL = 50pF CL = 50pF CL = 50pF Input Capacitance Maximum Clock Frequency Power Dissipation Capacitance (Note 3, 4) CIN fMAX CPD CL = 50pF CL = 15pF CL = 15pF 25oC VCC (V) 2 4.5 5 6 2 4.5 5 6 2 4.5 5 6 2 4.5 6 5 5 60 33 MIN TYP 20 20 12 MAX 240 48 41 240 48 41 150 30 26 75 15 13 10 -40oC TO 85oC MIN MAX 300 60 51 300 60 51 190 38 33 95 19 16 10 -55oC TO 125oC MIN MAX 360 72 61 360 72 61 225 45 38 110 22 19 10 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF MHz pF
PARAMETER HC TYPES Propagation Delay CP to Qn
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