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Part: CDC351IDWR
Category:
Timing Circuits
-> Clock Buffers
-> Non-PLL
Description: ti CDC351, 1-Line to 10-Line 3.3V Clock Driver With Tri-state Outputs
Company: Texas Instruments, Inc.
Datasheet: Download CDC351IDWR datasheet File size : 758 kB
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Datasheet text preview:
CDC351. CDC351I 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS
www.ti.com
SCAS441D FEBRUARY 1994 REVISED OCTOBER 2003
FEATURES
· Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC LVTTL-Compatible Inputs and Outputs Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Distributes One Clock Input to Ten Outputs Distributed VCC and Ground Pins Reduce Switching Noise High-Drive Outputs (32-mA IOH, 32-mA IOL) State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages
DB OR DW PACKAGE (TOP VIEW)
· · · · · · · ·
GND Y10 VCC Y9 OE A P0 P1 Y8 VCC Y7 GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
GND Y1 VCC Y2 GND Y3 Y4 GND Y5 VCC Y6 GND
DESCRIPTION
The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE) input disables the outputs to a high-impedance state. The CDC351 operates at nominal 3.3-V VCC. The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to GND. FUNCTION TABLE
INPUTS A L H L H OE H H L L OUTPUTS Yn Z Z L H
AVAILABLE OPTIONS
TA 0°C to 70°C 40°C to 85°C (1) Shrink Small-Outline Package (DB) (1) CDC351DB CDC351IDB Small-Outline Package (DW) (1) CDC351DW CDC351IDW
This package is available tape and reel. Order by adding an R to the orderable part number (e.g., CDC351DBR).
EPIC-IIB is a trademark of Texas Instruments. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1994 2003, Texas Instruments Incorporated
CDC351. CDC351I 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS441D FEBRUARY 1994 REVISED OCTOBER 2003
www.ti.com
LOGIC SYMBOL
5 OE EN
A
23 21 19 18 A 6 16 14 11 9 4 2
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10
Note A: This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
LOGIC DIAGRAM (POSITIVE LOGIC)
OE 5
23
Y1
21
Y2
19
Y3
18 A 6 16 78 P0 P1 14
Y4
Y5
Y6
11
Y7
9
Y8
4
Y9
2
Y10
2
www.ti.com
CDC351. CDC351I 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS441D FEBRUARY 1994 REVISED OCTOBER 2003
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage range, VCC Input voltage range, VI (2) Voltage range applied to any output in the high state or power-off state, Current into any output in the low state, IO Input clamp current, IIK(VI < 0) Output clamp current, IOK (VI < 0) Package thermal impedance JA (3): Storage temperature range, Tstg (1) DB package DW package VO (2) 0.5 V to 4.6 V 0.5 V to 7 V 0.5 V to 3.6 V 64 mA 18 mA 50 mA 147°C/ W 101°C/ W 65°C to 150°C
(2) (3)
Stresses beyond those listed under,, absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The package thermal impedance is calculated in accordance with JESD51.
RECOMMENDED OPERATING CONDITIONS (1)
MIN VCC VIH VIL VI IOH IOL fclock TA Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input clock frequency Operating free-air temperature Commercial Industrial 0 40 0 3 2 0.8 5.5 32 32 100 70 85 MAX 3.6 UNIT V V V V mA mA MHz °C °C
(1)
Unused pins (input or I/O) must be held high or low.
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL II IO (1) IOZ ICC Ci Co (1) TEST CONDITIONS VCC = 3 V, VCC = 3 V, VCC = 3 V, VCC = 3.6 V, VCC = 3.6 V, VCC = 3.6 V, II = 18 mA IOH = 32 mA IOL = 32 mA VI = VCC or GND VO = 2.5 V VO = 3 V or 0 Outputs high VCC = 3.6 V, IO = 0, VI = VCC or GND VI = VCC or GND, VO = VCC or GND, VCC = 3.3 V, VCC = 3.3 V, Outputs low Outputs disabled f = 10 MHz f = 10 MHz 4 6 15 2 0.5 ±1 150 ±10 0.3 25 0.3 pF pF mA MIN TYP MAX 1.2 UNIT V V V µA mA µA
Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 3
CDC351. CDC351I 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS441D FEBRUARY 1994 REVISED OCTOBER 2003
www.ti.com
SWITICHING CHARACTERISTICS
CL = 50 pF (see Figure 1 and Figure 2)
PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ tsk(o) tsk(p) tsk(pr) tr tf FROM (INPUT) A OE OE A A A A A TO (OUTPUT) Y Y Y Y Y Y Y Y VCC = 3.3 V, TA = 25°C MIN 3.2 3 1.8 1.8 1.8 1.8 TYP 3.7 3.5 3.8 3.8 3.9 4.2 0.3 0.2 MAX 4.2 4 5.5 5.5 5.9 5.9 0.5 0.8 1 1.3 1.3 1.7 1.7 5.9 5.9 6.3 6.4 0.5 0.8 1 1.5 1.5 1.1 1.1 1.5 1.5 6.1 6.1 6.5 6.6 0.6 0.9 1.1 1.5 1.5 VCC = 3 V to 3.6 V, TA = 0°C to 70°C MIN MAX VCC = 3 V to 3.6 V, TA = -40°C to 85°C MIN MAX ns ns ns ns ns ns ns ns UNIT
SWITCHING CHARACTERISTICS TEMPERATURE AND VCC COEFFICIENTS
over recommended operating free-air temperature and VCC range (1)
PARAMETER §tPLH(T) §tPHL(T) §tPLH(VCC) §tPHL(VCC) (1) (2) (3) Average temperature coefficient of low to high propagation delay Average temperature coefficient of high to low propagation delay Average VCC coefficient of low to high propagation delay Average VCC coefficient of high to low propagation delay FROM (INPUT) A A A A TO (OUTPUT) Y Y Y Y MIN MAX 65 (2) 45 (2) 140 (3) 120 (3) UNIT ps/10°C ps/10°C ps/ 100 mV ps/ 100 mV
These data were extracted from characterization material and are not tested at the factory. §tPLH(T) and §tPHL(T) are virtually independent of VCC. §tPLH(VCC) and §tPHL(VCC) are virtually independent of temperature.
4
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CDC351. CDC351I 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS441D FEBRUARY 1994 REVISED OCTOBER 2003
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH /tPHL tPLZ /tPZL tPHZ /tPZH S1 Open 6V GND
tw LOAD CIRCUIT Input 3V Timing Input 1.5 V 0V tsu Data Input 1.5 V VOLTAGE WAVEFORMS th 3V 1.5 V 0V Output Control (low-level enabling) tPZL 1.5 V 1.5 V 0V tPLZ 3V 1.5 V tPHZ VOH 1.5 V VOH - 0.3 V 0V VOLTAGE WAVEFORMS VOL + 0.3 V VOL 3V VOLTAGE WAVEFORMS 1.5 V 1.5 V 0V 3V
3V Input tPLH 1.5 V 1.5 V 0V tPHL 2V 0.8 V tr 2V 0.8 V VOH VOL Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B)
Output
1.5 V tf
tPZH
VOLTAGE WAVEFORMS
A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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