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Part: CDC392DR
Category:
Timing Circuits
-> Clock Buffers
-> Non-PLL
Description: ti CDC392, 1-To-6 Clock Driver With Selectable Polarity
Company: Texas Instruments, Inc.
Datasheet: Download CDC392DR datasheet File size : 758 kB
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Datasheet text preview:
CDC392 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS
SCAS335A DECEMBER 1992 REVISED NOVEMBER 1995
D D D D D D D D
Low Output Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Distributes One Clock Input to Six Clock Outputs Polarity Control Selects True or Complementary Outputs Distributed VCC and GND Pins Reduce Switching Noise High-Drive Outputs ( 32-mA IOH, 32-mA IOL) State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Packaged In Plastic Small-Outline Package
D PACKAGE (TOP VIEW)
GND 1Y2 1Y3 GND 2Y1 2Y2 GND 3Y1
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
1Y1 1T/C VCC 2T/C A VCC 3T/C OE
description
The CDC392 contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew for clock distribution. Through the use of the polarity-control (T/C) inputs, various combinations of true and complementary outputs can be obtained. The output-enable (OE) input is provided to disable the outputs to a high-impedance state. The CDC392 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE INPUTS OE H L L L L T/C X L L H H A X L H L H OUTPUT Y Z L H H L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-B is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1995, Texas Instruments Incorporated
POST OFFICE BOX 655303
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1
CDC392 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS
SCAS335A DECEMBER 1992 REVISED NOVEMBER 1995
logic symbol
OE 9 EN 16 2 3 5 6 8
1 A 1T/C 2T/C 3T/C 12 15 13 10 N1 N2 N3 1 1 2 2 3 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1Y1 1Y2 1Y3 2Y1 2Y2 3Y1
logic diagram (positive logic)
OE 1T/C 9 15 16 1Y1
2
1Y2
3 A 12 5 13 2T/C 6
1Y3
2Y1
2Y2
3T/C
10
8
3Y1
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CDC392 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS
SCAS335A DECEMBER 1992 REVISED NOVEMBER 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO . . . . . . . 0.5 V to VCC + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.77 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 300 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
MIN VCC VIH VIL VI IOH IOL t / v fclock TA Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Input clock frequency Operating free-air temperature 40 0 4.75 2 0.8 VCC 32 32 5 90 85 NOM 5 MAX 5.25 UNIT V V V V mA mA ns / V MHz °C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
CDC392 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS
SCAS335A DECEMBER 1992 REVISED NOVEMBER 1995
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL II IOZ ICC Ci VCC = 4.75 V, VCC = 4.75 V, VCC = 4.75 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5 25 V 5.25 V, or GND VI = VCC or GND VI = 2.5 V or 0.5 V VO = VCC or GND TEST CONDITIONS II = 18 mA IOH = 32 mA IOL = 32 mA VI = VCC or GND VO = VCC or GND Outputs high IO = 0 0, Outputs low Outputs disabled 3 7 MIN 3.85 0.55 ±1 ± 50 10 40 10 pF pF mA TYP MAX 1.2 UNIT V V V µA µA
Co All typical values are at VCC = 5 V, TA = 25°C
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figures 1 and 2)
PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tsk(o) tr tf FROM (INPUT) A TO (OUTPUT) Any Y Any Y Any Y Any Y Any Y (same phase) Any Y (any phase) 1.4 0.83 MIN 2 1.5 1.5 1.5 1.5 3 1.5 1.5 TYP MAX 6.5 5 5 5 6 8 5 5 0.6 2.2 UNIT ns ns ns ns ns ns ns
T/C OE OE A
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CDC392 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS
SCAS335A DECEMBER 1992 REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
2 × VCC From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 × VC C Open
LOAD CIRCUIT FOR OUTPUTS
Output Control (low-level enabling) tPZL 3V
3V 1.5 V 1.5 V 0V tPLZ VC C 50% VCC tPHZ VOH 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL + 0.3 V VOL
Input 1.5 V tPLH 70% VCC 30% VCC tr 50% VCC tf VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V
0V tPHL V 70% VCC OH 30% VCC VOL
Output Waveform 1 S1 at 2 × VCC (see Note C) Output Waveform 2 S1 at Open (see Note C) tPZH
Output
50% VCC
NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
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