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Part: CDC509PW
Category:
Logic
-> Clock Drivers/Distribution
Description: 3.3-v Phase-lock Loop Clock Driver
Company: Texas Instruments, Inc.
Datasheet: Download CDC509PW datasheet File size : 758 kB
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Datasheet text preview:
CDC509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS576B JULY 1996 REVISED JANUARY 1998
D D D D D D D
Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Pin Is Used to Synchronize the Outputs to the Clock Input No External RC Network Required Operates at 3.3-V VCC Packaged in Plastic 24-Pin Thin Shrink Small-Outline Package
PW PACKAGE (TOP VIEW)
description
AGND VCC 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 VCC 1G FBOUT
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
CLK AVCC VCC 2Y0 2Y1 GND GND 2Y2 2Y3 VCC 2G FBIN
The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3-V VCC and is designed to drive up to five clock loads per output. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDC509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. The CDC509 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE INPUTS 1G X L L H H 2G X L H L H CLK L H H H H 1Y (0:4) L L L H H OUTPUTS 2Y (0:3) L L H L H FBOUT L H H H H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
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1
CDC509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS576B JULY 1996 REVISED JANUARY 1998
functional block diagram
1G 11
3
1Y0
4
1Y1
5
1Y2
8
1Y3
9 14
1Y4
2G
21
2Y0
20
2Y1
CLK
24
17
FBIN
13
AVCC
23
2
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÁÁÁÁÁÎ ÎÎÎÎÎÁ ÎÁÁÁÁÁÎ ÎÎÎÎÎÁ
PLL AVAILABLE OPTIONS PACKAGE TA 0°C to 70°C SMALL OUTLINE (PW) CDC509PWR
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2Y2
16
2Y3
12
FBOUT
· DALLAS, TEXAS 75265
CDC509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS576B JULY 1996 REVISED JANUARY 1998
Terminal Functions
TERMINAL NAME NO. TYPE DESCRIPTION Clock input. CLK provides the clock signal to be distributed by the CDC509 clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4) are disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same frequency as CLK. Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same frequency as CLK. Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via the 1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control input. Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via the 2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control input. Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. Analog ground. AGND provides the ground reference for the analog circuitry. Power supply Ground
CLK
24
I
FBIN
13
I
1G
11
I
2G
14
I
FBOUT 1Y(0:4) 2Y(0:3)
12 3, 4, 5, 8, 9 16, 17, 20 21
O O O
AVCC AGND VCC GND
23 1 2, 10, 15, 22 6, 7, 18, 19
Power Ground Power Ground
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002.
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3
CDC509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS576B JULY 1996 REVISED JANUARY 1998
recommended operating conditions (see Note 4)
MIN VCC VIH VIL VI IOH IOL Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current 0 0 3 2 0.8 VCC 20 20 70 MAX 3.6 UNIT V V V V mA mA °C
TA Operating free-air temperature NOTE 4: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL II ICC ICC Ci Co II = 18 mA IOH = 100 µA IOH = 20 mA IOL = 100 µA IOL = 20 mA VI = VCC or GND VI = VCC or GND, One input at VCC 0.6 V, VI = VCC or GND VO = VCC or GND IO = 0, Outptus high or low Other inputs at VCC or GND TEST CONDITIONS VCC 3V MIN to MAX 3V MIN to MAX 3V 3.6 V 3.6 V 3.3 V to 3.6 V 3.3 V 3.3 V 4 6 VCC0.2 2.4 0.2 0.55 ±5 10 500 MIN TYP MAX 1.2 UNIT V V V µA µA µA pF pF
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. For ICC of AVCC, see Figure 5.
timing requirements over recommended ranges of supply voltage and operating free-air temperature
MIN fclock Clock frequency Input clock duty cycle Stabilization time§ 25 40% MAX 125 60% UNIT MHz
1 ms § Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable.
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CDC509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS576B JULY 1996 REVISED JANUARY 1998
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 30 pF (see Note 5 and Figures 1 and 2)
PARAMETER tphase error, reference (see Figure 3) tphase error, jitter, (see Note 6) tsk(o) Jitter(pk-pk) Duty cycle, reference y, (see Figure 4) tr tf FROM (INPUT) 66 MHz 66 MHz) F(clkin 66 MHz) F(clkin > 66 MHz) TO (OUTPUT) FBIN FBIN Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT 1.1 0.8 1.5 1.3 100 45% 43% 0.7 0.5 220 480 VCC = 3.3 V ± 0.165 V MIN TYP MAX MIN VCC = 3.3 V ± 0.3 V TYP 100...480 340 200 100 55% 57% 1.6 1.5 ns ns MAX ps ps ps ps UNIT
This parameters are not production tested. The tsk(o) specification is only valid for equal loading of all outputs. NOTES: 5. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 6. Phase error does not include jitter. The total phase error is 120 ps to 580 ps for the 5% VCC range.
PARAMETER MEASUREMENT INFORMATION
3V Input tpd From Output Under Test 30 pF 500 W Output 2V 0.4 V tr LOAD CIRCUIT FOR OUTPUTS 50% VCC tf 2V 0.4 V VOH VOL 50% VCC 0V
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 100 MHz, ZO = 50 , tr 1.2 ns, tf 1.2 ns. C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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