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Part: CDC516
Category:
Communication
-> Freq/Signal Converters/Generators
Description: 3.3v Phase-lock Loop Clock Driver
Company: Texas Instruments, Inc.
Datasheet: Download CDC516 datasheet File size : 758 kB
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Datasheet text preview:
CDC516 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A JULY 1996 REVISED JANUARY 1998
D D D D D D D
Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to Four Banks of Four Outputs Separate Output Enable for Each Output Bank External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input No External RC Network Required Operates at 3.3-V VCC Packaged in Plastic 48-Pin Thin Shrink Small-Outline Package
DGG PACKAGE (TOP VIEW)
description
The CDC516 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback output (FBOUT) to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC516 operates at 3.3-V VCC and is designed to drive up to five clock loads per output. Four banks of four outputs provide 16 low-skew, low-jitter copies of the input clock. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at the input clock. Each bank of outputs can be enabled or disabled separately via the 1G, 2G, 3G, and 4G control inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
VCC 1Y0 1Y1 GND GND 1Y2 1Y3 VCC 1G GND AVCC CLK AGND AGND GND 2G VCC 2Y0 2Y1 GND GND 2Y2 2Y3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VCC 4Y0 4Y1 GND GND 4Y2 4Y3 VCC 4G GND AVCC FBIN AGND FBOUT GND 3G VCC 3Y0 3Y1 GND GND 3Y2 3Y3 VCC
Unlike many products containing PLLs, the CDC516 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDC516 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL may be bypassed for test purposes by strapping AVCC to ground. The CDC516 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
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1
CDC516 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A JULY 1996 REVISED JANUARY 1998
FUNCTION TABLE INPUTS 1G X L L L L L L L L H H H H H H H H 2G X L L L L H H H H L L L L H H H H 3G X L L H H L L H H L L H H L L H H 4G X L H L H L H L H L H L H L H L H CLK L H H H H H H H H H H H H H H H H 1Y (0:3) L L L L L L L L L H H H H H H H H 2Y (0:3) L L L L L H H H H L L L L H H H H OUTPUTS 3Y (0:3) L L L H H L L H H L L H H L L H H 4Y (0:3) L L H L H L H L H L H L H L H L H FBOUT L H H H H H H H H H H H H H H H H
AVAILABLE OPTIONS PACKAGE TA 0°C to 70°C SMALL OUTLINE (PW) CDC516DGGR
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CDC516 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A JULY 1996 REVISED JANUARY 1998
functional block diagram
1G 9
2
1Y0
3
1Y1
6
1Y2
7 2G 16
1Y3
18
2Y0
19
2Y1
22
2Y2
23 3G 33
2Y3
31
3Y0
30
3Y1
27
3Y2
26 4G 40
3Y3
47
4Y0
CLK
12
FBIN
37
AVCC
11
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÁÁÁÁÁÁÁ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
PLL
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46
4Y1
43
4Y2
42
4Y3
35
FBOUT
· DALLAS, TEXAS 75265
3
CDC516 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A JULY 1996 REVISED JANUARY 1998
Terminal Functions
TERMINAL NAME NO. TYPE DESCRIPTION Clock input. CLK provides the clock signal to be distributed by the CDC516 clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. Output bank enable. 1G is the output enable for outputs 1Y(0:3). When 1G is low, outputs 1Y(0:3) are disabled to a logic-low state. When 1G is high, all outputs 1Y(0:3) are enabled and switch at the same frequency as CLK. Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are disabled to a logic-low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same frequency as CLK. Output bank enable. 3G is the output enable for outputs 3Y(0:3). When 3G is low, outputs 3Y(0:3) are disabled to a logic-low state. When 3G is high, all outputs 3Y(0:3) are enabled and switch at the same frequency as CLK. Output bank enable. 4G is the output enable for outputs 4Y(0:3). When 4G is low, outputs 4Y(0:3) are disabled to a logic-low state. When 4G is high, all outputs 4Y(0:3) are enabled and switch at the same frequency as CLK. Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. Clock outputs. These outputs provide low-skew copies of CLK. Outputs 1Y(0:3) are enabled via 1G. These outputs can be disabled to a logic-low state by deasserting the 1G control input. Clock outputs. These outputs provide low-skew copies of CLK. Outputs 2Y(0:3) are enabled via 2G. These outputs can be disabled to a logic-low state by deasserting the 2G control input. Clock outputs. These outputs provide low-skew copies of CLK. Outputs 3Y(0:3) are enabled via 3G. These outputs can be disabled to a logic-low state by deasserting the 3G control input. Clock outputs. These outputs provide low-skew copies of CLK. Outputs 4Y(0:3) are enabled via 4G. These outputs can be disabled to a logic-low state by deasserting the 4G control input. Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, the PLL is bypassed and CLK is buffered directly to the device outputs. Analog ground. AGND provides the ground reference for the analog circuitry. Power supply
CLK
12
I
FBIN
37
I
1G
9
I
2G
16
I
3G
33
I
4G
40
I
FBOUT 1Y(0:3) 2Y(0:3) 3Y(0:3) 4Y(0:3)
35 2, 3, 6, 7 18, 19, 22, 26 31, 30, 27, 26 47, 46, 43, 42
O O O O O
AVCC AGND VCC GND
11, 38 13, 14, 36 1, 8, 17, 24, 25, 32, 41, 48 4, 5, 10, 15, 20, 21, 28, 29, 34, 39, 44, 45
Power Ground Power
Ground
Ground
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CDC516 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A JULY 1996 REVISED JANUARY 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.85 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002.
recommended operating conditions (see Note 4)
MIN VCC VIH VIL VI IOH IOL Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current 0 0 3 2 0.8 VCC 20 20 70 MAX 3.6 UNIT V V V V mA mA °C
TA Operating free-air temperature NOTE 4: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL II ICC§ ICC Ci II = 18 mA IOH = 100 µA IOH = 20 mA IOL = 100 µA IOL = 20 mA VI = VCC or GND VI = VCC or GND One input at VCC 0.6 V, VI = VCC or GND VO = VCC or GND IO = 0, Outputs: low or high Other inputs at VCC or GND TEST CONDITIONS VCC 3V MIN to MAX 3V MIN to MAX 3V 3.6 V 3.6 V 3.3 V to 3.6 V 3.3 V 4 6 VCC 0.2 2.4 0.2 0.55 ±5 20 500 MIN TYP MAX 1.2 UNIT V V V µA µA µA pF pF
Co 3.3 V For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. § For ICC of AVCC, see Figure 5. For dynamic digital ICC, see Figure 6.
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