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Part: CDC536DBR
Category:
Timing Circuits
-> PLL (Phase locked loop)
-> PLL-Based Synthesizers
Description: ti CDC536, 3.3V PLL Clock Driver With 1/2x, 1x And 2x Frequency Options
Company: Texas Instruments, Inc.
Datasheet: Download CDC536DBR datasheet File size : 758 kB
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Datasheet text preview:
CDC536 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS378F APRIL 1994 REVISED OCTOBER 1998
D D D D D D D D D D D D D
Low-Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC Distributes One Clock Input to Six Outputs One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency No External RC Network Required External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input Application for Synchronous DRAM, High-Speed Microprocessor Negative-Edge-Triggered Clear for Half-Frequency Outputs TTL-Compatible Inputs and Outputs Outputs Drive 50- Parallel-Terminated Transmission Lines State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Distributed VCC and Ground Pins Reduce Switching Noise Packaged in Plastic 28-Pin Shrink Small Outline Package
DB OR DL PACKAGE (TOP VIEW)
AVCC AGND CLKIN SEL OE GND 1Y1 VCC GND 1Y2 VCC GND 1Y3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
AVCC AGND FBIN TEST CLR VCC 2Y1 GND VCC 2Y2 GND VCC 2Y3 GND
description
The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V VCC and is designed to drive a 50-W transmission line. The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to the input clock (CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN. The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at the input clock. Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state. When OE is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass the PLL. TEST should be strapped to GND for normal operation. Unlike many products containing PLLs, the CDC536 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-B is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
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1
CDC536 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS378F APRIL 1994 REVISED OCTOBER 1998
description (continued)
Because it is based on PLL circuitry, the CDC536 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN as well as following any changes to the PLL reference or feedback signals. Such changes occur upon change of the select inputs, enabling the PLL via TEST, and upon enable of all outputs via OE. The CDC536 is characterized for operation from 0°C to 70°C.
detailed description of output configurations
The voltage-controlled oscillator (VCO) in the CDC536 has a frequency range of 100 MHz to 200 MHz, twice the operating frequency range of the CDC536 outputs. The output of the VCO is divided by two and by four to provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO frequency. The SEL0 and SEL1 inputs determine which of the two signals are buffered to each bank of device outputs. One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the frequency of this output matches that of the CLKIN signals. In the case that a VCO/2 output is wired to FBIN, the VCO must operate at twice the CLKIN frequency, resulting in device outputs that operate at the same or one-half the CLKIN frequency. If a VCO/4 output is wired to FBIN, the device outputs operate at the same or twice the CLKIN frequency. output configuration A Output configuration A is valid when any output configured as a 1× frequency output in Table 1 is fed back to the FBIN input. The input frequency range for the CLKIN input is 50 MHz to 100 MHz when using output configuration A. Outputs configured as 1/2× outputs operate at half the CLKIN frequency, while outputs configured as 1× outputs operate at the same frequency as the CLKIN input. Table 1. Output Configuration A
INPUTS SEL L H NOTE: n = 1, 2, 3 OUTPUTS 1/2× FREQUENCY None 1Yn 1× FREQUENCY All 2Yn
output configuration B Output configuration B is valid when any output configured as a 1× frequency output in Table 2 is fed back to FBIN. The input frequency range for the CLKIN input is 25 MHz to 50 MHz when using output configuration B. Outputs configured as 1× outputs operate at the CLKIN frequency, while outputs configured as 2× outputs operate at double the frequency of the CLKIN input. Table 2. Output Configuration B
INPUTS SEL L H NOTE: n = 1, 2, 3 OUTPUTS 1× FREQUENCY All 1Yn 2× FREQUENCY None 2Yn
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CDC536 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS378F APRIL 1994 REVISED OCTOBER 1998
functional block diagram
OE 5
24 CLR 26
Phase-Lock Loop
3 CLKIN
TEST
25
SEL
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
ÁÁÁ ÁÁÁ ÁÁÁ
B2
7 1Y1 10 1Y2 13 1Y3 22 2Y1 19 2Y2 16 2Y3 3
FBIN
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÁÁÎÎÎÎÎÎÎ Á ÁÁÎÎÎÎÎÎÎ ÁÁÁÁÁÁÁ ÁÁÎÎÎÎÎÎÎ Á
B2
CDC536 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS378F APRIL 1994 REVISED OCTOBER 1998
Terminal Functions
TERMINAL NAME NO. I/O DESCRIPTION Clock input. CLKIN provides the clock signal to be distributed by the CDC536 clock-driver circuit. CLKIN is used to provide the reference signal to the integrated phase-lock loop that generates the clock output signals. CLKIN must have a fixed frequency and fixed phase in order for the phase-lock loop to obtain phase lock. Once the circuit is powered up and a valid CLKIN signal is applied, a stabilization time is required for the phase-lock loop to phase lock the feedback signal to its reference signal. CLR is used for testing purposes only. Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to one of the six clock outputs to provide frequency and phase lock. The internal PLL adjusts the output clocks to obtain zero phase delay between the FBIN and differential CLKIN inputs. Output enable. OE is the output enable for all outputs. When OE is low, all outputs are enabled. When OE is high, all outputs are in the high-impedance state. Since the feedback signal for the phase-lock loop is taken directly from an output, placing the outputs in the high-impedance state interrupts the feedback loop; therefore, when a high-to-low transition occurs at OE, enabling the output buffers, a stabilization time is required before the phase-lock loop obtains phase lock. Output configuration select. SEL selects the output configuration for each output bank (e.g. 1×, 1/2×, or 2×). (see Tables 1 and 2). TEST is used to bypass the phase-lock loop circuitry for factory testing of the device. When TEST is low, all outputs operate using the PLL circuitry. When TEST is high, the outputs are placed in a test mode that bypasses the PLL circuitry. TEST should be grounded for normal operation. These outputs are configured by SEL to transmit one-half or one-fourth the frequency of the VCO. The relationship between the CLKIN frequency and the output frequency is dependent on SEL. The duty cycle of the Y output signals is nominally 50%, independent of the duty cycle of the CLKIN signal. These outputs transmit one-half the frequency of the VCO. The relationship between the CLKIN frequency and the output frequency is dependent on the frequency of the output being fed back to FBIN. The duty cycle of the Y output signals is nominally 50% independent of the duty cycle of the CLKIN signal.
CLKIN
3
I
CLR FBIN
24 26
I I
OE
5
I
SEL
4
I
TEST
25
I
1Y1 1Y3
7, 10, 13
O
2Y1 2Y3
22, 19, 16
O
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CDC536 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS378F APRIL 1994 REVISED OCTOBER 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . 0.5 V to 5.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . . 0.68 W DL package . . . . . . . . . . . . . . . . . . . . 0.7 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 75 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002.
recommended operating conditions (see Note 3)
MIN VCC VIH VIL VI IOH IOL Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current 0 0 3 2 0.8 5.5 32 32 70 MAX 3.6 UNIT V V V V mA mA °C
TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL II IOZH IOZL ICC Ci VCC = 3 V, VCC = MIN to MAX, VCC = 3 V, VCC = 3 V, VCC = 3 V, VCC = 0 or MAX, VCC = 3.6 V, VCC = 3.6 V, VCC = 3.6 V, VCC = 3.6 V, 36V VI = VCC or GND or GND VI = VCC or GND VO = VCC or GND TEST CONDITIONS CONDITIONS II = 18 mA IOH = 100 µA IOH = 32 mA IOL = 100 µA IOL = 32 mA VI = 3.6 V VI = VCC or GND VO = 3 V VO = 0 Outputs high IO = 0 0, Outputs low Outputs disabled TA = 25°C MIN MAX 1.2 VCC 0.2 2 0.2 0.5 ±10 ±1 10 10 2 2 2 6 9 pF pF mA UNIT V V V µA µA µA
Co For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
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5
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