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Part: CDC5801
Category:
Timing Circuits
-> PLL (Phase locked loop)
Description: Low Jitter PLL Based Multiplier/divider With Programmable Delay Lines Down to Sub 10ps
Company: Texas Instruments, Inc.
Datasheet: Download CDC5801 datasheet File size : 758 kB
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Datasheet text preview:
CDC5801 LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT
SCAS682A OCTOBER 2002
D Low Jitter Clock Multiplier by x4, x6, x8.
Input Frequency Range (19 MHz to 125 MHz). Supports Output Frequency From 150 MHz to 500 MHz Low Jitter Clock Divider by /2, /3, /4. Input Frequency Range (50 MHz to 125 MHz). Supports Ranges of Output Frequency From 12.5 MHz to 62.5 MHz 2.6 mUI Programmable Bidirectional Delay Steps Typical 8.0-ps Phase Jitter (12 kHz to 20 MHz) @ 500 MHz Typical 2.1-ps RMS Period Jitter (Entire Frequency Band) @ 500 MHz One Single-Ended Input and One Differential Output Pair Output Can Drive LVPECL, LVDS, and LVTTL Three Power Operating Modes to Minimize Power Low Power Consumption (Typical 200 mW at 500 MHz) Packaged in a Shrink Small-Outline Package (DBQ) No External Components Required for PLL Spread Spectrum Clock Tracking Ability to Reduce EMI
D Applications: Video Graphics, Gaming
Products, Datacom, Telecom
D Accepts LVCMOS, LVTTL Inputs for D
REFCLK Terminal Accepts Other Single-Ended Signal Levels at REFCLK Terminal by Programming Proper VDDREF Voltage Level (For Example, HSTL 1.5 if VDDREF = 1.6 V) Supports Industrial Temperature Range of 40°C to 85°C
DBQ PACKAGE (TOP VIEW)
D
D D D D D D D D D D
D
VDDREF REFCLK VDDP GNDP GND LEADLAG DLYCTRL GNDPA VDDPA VDDPD STOPB PWRDNB
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
P0 P1 VDDO GNDO CLKOUT NC CLKOUTB GNDO VDDO MULT0/DIV0 MULT1/DIV1 P2
NC No internal connection
description
The CDC5801 device provides clock multiplication and division from a single-ended reference clock (REFCLK) to a differential output pair (CLKOUT/CLKOUTB). The multiply and divide terminals (MULT/DIV0:1) provide selection for frequency multiplication and division ratios, generating CLKOUT/CLOUTKB frequencies ranging from 12.5 MHz to 500 MHz with a clock input reference (REFCLK) ranging from 19 MHz to 125 MHz. Please see Table 1 and Table 2 for detail frequency support. The implemented phase aligner provides the possibility to phase align (zero delay) between CLKOUT/CLKOUTB and REFCLK or any other CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG terminals. The phase aligner also allows the user to delay or advance the CLKOUT/CLKOUTB with steps of 2.6 mUI (unit interval). For every rising edge on the DLYCTRL terminal the output clocks are delayed by 2.6-mUI step size as long as there is low on the LEADLAG terminal. Similarly for every rising edge on the DLYCTRL terminal the output clocks are advanced by 2.6-mUI step size as long as there is high on the LEADLAG terminal. As the phase between REFCLK and CLKOUT/CLKOUTB is random after power up, the application may implement a self calibration routine at power up to produce a certain phase start position, before programming a fixed delay with the clock on the DLYCTRL terminal.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
CDC5801 LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT
SCAS682A OCTOBER 2002
Depending on the selection of the mode terminals (P0:2), the device behaves as a multiplier (by 4, 6, or 8) with the phase aligner bypassed or as a multiplier or divider with programmable delay and phase aligner functionality. Through the select terminals (P0:2) user can also bypass the phase aligner and the PLL (test mode) and output the REFCLK directly on the CLKOUT/CLKOUTB terminals. Through P0:2 terminals the outputs could be in a high impedance state. This device has another unique capability to be able to function with a wide band of voltages on the REFCLK terminal by varying the voltage on the VDDREF terminal. The CDC5801 device is characterized for operation over free-air temperatures of 40°C to 85°C.
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CDC5801 LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT
SCAS682A OCTOBER 2002
functional block diagram
PWRDWNB P0 P1 P2 STOPB
Control Logic
PLLCLK Phase Aligner Bypass MUX REFCLK PLL B Phase Aligner Divider Ratio CLKOUT CLKOUTB
VDDREF/2 D A
VDDPD/2
2
MULT0/DIV0 MULT1/DIV1
DLYCTRL
LEADLAG
FUNCTION TABLE MODE Multiplication with programmable delay and phase alignment active Division with programmable delay and phase alignment active Multiplication only mode (phase aligner bypassed) § Test mode P0 0 P1 0 P2 0 CLKOUT/CLKOUTB REFCLK multiplied by ratio per Table 1 selected by MULT/DIV terminals. Outputs are delayed or advanced based on DLYCTRL and LEADLAG terminal configuration. REFCLK divided by ratio per Table 2 selected by MULT/DIV terminals. Outputs are delayed or advanced based on DLYCTRL and LEADLAG terminal configuration. In this mode one can only multiply as per Table 1. Programmable delay capability and divider capability is deactivated. PLL is running. PLL and phase aligner both bypassed. REFCLK is directly channeled to output.
0
0
1
1 1
0 1
0 0
Hi-Z mode 0 1 X Hi-Z X = don't care, Hi-Z = high impedance Please see Table 4 and Table 5 for explanation for the programmability and phase alignment functions. § In this mode the DLYCTRL and LEADLAG terminals must be strapped high or low. Lowest possible jitter is achieved in this mode, but a delay of 200 ps to 2 ns expected typically from REFCLK to CLKOUT depending on the output frequency.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
CDC5801 LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT
SCAS682A OCTOBER 2002
Terminal Functions
TERMINAL NAME CLKOUT CLKOUTB DLYCTRL NO. 20 18 7 I/O O O I Output clock Output clock (complement) Every rising edge on this terminal delays/advances the CLKOUT/CLKOUTB signal by 1/384th of the CLKOUT/CLKOUTB period. (e.g., for a 90 degree delay or advancement one needs to provide 96 rising edges). See Table 4. GND for VDDREF and VDDPD GND for clock output terminals (CLKOUT, CLKOUTB) GND for PLL GND for phase aligner I I I I I I I I I I I I I I Decides if the output clock is delayed or advanced with respect to REFCLK. See Table 4. PLL multiplier and divider select PLL multiplier and divider select Not used Active low power down state, CLKOUT/CLKOUTB goes low Mode control, see Function Table Mode control, see Function Table Mode control, see Function Table Reference input clock Active low output disabler, PLL and PA still running, CLKOUT and CLKOUTB goes to a dc value as per Table 3 Supply voltage for phase aligner Reference voltage for the DLYCTRL, LEADLAG terminals and STOPB function Reference voltage for REFCLK Supply voltage for the output terminals (CLKOUT, CLKOUTB) Supply voltage for PLL DESCRIPTION
GND GNDO GNDP GNDPA LEADLAG MULT0/DIV0 MULT1/DIV1 NC PWRDNB P0 P1 P2 REFCLK STOPB VDDPA VDDPD VDDREF VDDO VDDP
5 17, 21 4 8 6 15 14 19 12 24 23 13 2 11 9 10 1 16, 22 3
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CDC5801 LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT
SCAS682A OCTOBER 2002
PLL divider/multiplier selection
Table 1 and Table 2 list the supported REFCLK and BUSCLK (CLKOUT/CLKOUTB) frequencies. Table 1. Multiplication Ratios (P0:2 = 000 or 100)
MULT0 0 0 1 MULT1 0 1 1 REFCLK (MHZ) 38125 2583.3 1962.5 MULTIPLICATION RATIO 4 6 8 BUSCLK (MHZ) 152500 150500 152500
Table 2. Divider Ratio (P0:2 = 001)
MULT0 0 1 1 MULT1 0 0 1 REFCLK (MHZ) 100125 7593 5062 DIVISION RATIO 2 3 4 BUSCLK (MHZ) 5062.5 2531 12.515.5
Table 3. Clock Output Driver States
STATE Powerdown CLK stop Normal PWRDNB 0 1 1 STOPB X 0 1 CLKOUT GND VO, STOP As per Function Table CLKOUTB GND VO, STOP As per Function Table
Table 4. Programmable Delay and Phase Alignment
DLYCTRL Each rising edge Each rising edge LEADLAG 1 CLKOUT AND CLKOUTB Will be advanced by one step size (see Table 5)
0 Will be delayed by one step size (see Table 5) For every 32nd edge, there are one or two edges the phase aligner does not update. Therefore, CLKOUT phase is not updated on every 32nd edge.
Table 5. Clock Output Driver States
FUNCTIONALITY Multiply by 4, 6, 8 Divide by 2 Divide by 3 Divide by 4 STEP SIZE CLKOUT period/384 (for example, 6.5 ps @ 400 MHz) CLKOUT period/3072 (for example, 6.5 ps @ 50 MHz) CLKOUT period/6144 (for example, 6.5 ps @ 25 MHz) CLKOUT period/12288 (for example, 6.5 ps @ 12.5 MHz)
NOTE: The frequency of the DLYCTRL terminal must always be equal or less than the frequency of the LEADLAG terminal.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
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