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Part: CDC586PAH
Category:
Timing Circuits
-> PLL (Phase locked loop)
-> PLL-Based Synthesizers
Description: ti CDC586, 3.3V PLL Clock Driver With 1/2x, 1x And 2x Frequency Options
Company: Texas Instruments, Inc.
Datasheet: Download CDC586PAH datasheet File size : 758 kB
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Datasheet text preview:
CDC586 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS336D FEBRUARY 1993 REVISED OCTOBER 1998
D D D D D D
Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC Distributes One Clock Input to Twelve Outputs Two Select Inputs Configure Up to Nine Outputs to Operate at One-Half or Double the Input Frequency No External RC Network Required External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input
D D D D D D
Application for Synchronous DRAM, High-Speed Microprocessor TTL-Compatible Inputs and Outputs Outputs Drive Parallel 50- Terminated Transmission Lines State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Distributed VCC and Ground Pins Reduce Switching Noise Packaged in 52-Pin Thin Quad Flat Package
PAH PACKAGE (TOP VIEW)
GND 1Y1 VCC GND 1Y2 VCC GND 1Y3 VCC GND GND 2Y1 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26
GND SEL1 SEL0 AGND FBIN AGND AV CC CLKIN NC AV CC OE TEST CLR VC C 4Y3 GND VC C 4Y2 GND VC C 4Y1 GND GND VC C 3Y3 GND GND 2Y2 VCC GND 2Y3 VCC GND GND 3Y1 VCC
NC No internal connection
description
The CDC586 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC586 operates at 3.3-V VCC and is designed to drive a properly terminated 50-W transmission line.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-B is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
GND 3Y2 VCC
Copyright © 1998, Texas Instruments Incorporated
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CDC586 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS336D FEBRUARY 1993 REVISED OCTOBER 1998
description (continued)
The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to CLKIN. One of the twelve output clocks must be fed back to FBIN for the PLL to maintain synchronization between the CLKIN input and the outputs. The output used as the feedback pin is synchronized to the same frequency as the CLKIN input. The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. Select inputs (SEL1, SEL0) configure up to nine Y outputs, in banks of three, to operate at one-half or double the CLKIN frequency, depending on which pin is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLKIN. Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state. When OE is low, the outputs are active. TEST is used for factory testing of the device and can be used to bypass the PLL. TEST should be strapped to GND for normal operation. Unlike many products containing PLLs, the CDC586 does not require external RC networks. The loop filter for the PLL is included on chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDC586 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, as well as following any changes to the PLL reference or feedback signals. Such changes occur upon change of the select inputs, upon enabling of the PLL via TEST, and upon enable of all outputs via OE. The CDC586 is characterized for operation from 0°C to 70°C.
detailed description of output configurations
The voltage-controlled oscillator (VCO) used in the CDC586 PLL has a frequency range of 100 MHz to 200 MHz, twice the operating frequency range of the CDC586 outputs. The output of the VCO is divided by two and by four to provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO frequency. SEL0 and SEL1 select which of the two signals are buffered to each bank of device outputs. One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the frequency and phase of this output match that of the CLKIN signal. In the case that a VCO/2 output is wired to FBIN, the VCO must operate at twice the CLKIN frequency, resulting in device outputs that operate at either the same or one-half the CLKIN frequency. If a VCO/4 output is wired to FBIN, the device outputs operate at twice or the same frequency as the CLKIN frequency.
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CDC586 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS336D FEBRUARY 1993 REVISED OCTOBER 1998
output configuration A Output configuration A is valid when any output configured as a 1x frequency output in Table 1 is fed back to FBIN. The input frequency range for CLKIN is 50 MHz to 100 MHz when using output configuration A. Outputs configured as 1/2x outputs operate at half the CLKIN frequency, while outputs configured as 1x outputs operate at the same frequency as CLKIN. Table 1. Output Configuration A
INPUTS SEL1 L L H H SEL0 L H L H OUTPUTS 1/2x FREQUENCY None 1Yn 1Yn, 2Yn 1Yn, 2Yn, 3Yn 1x FREQUENCY All 2Yn, 3Yn, 4Yn 3Yn, 4Yn 4Yn
NOTE: n = 1, 2, 3
output configuration B Output configuration B is valid when any output configured as a 1x frequency output in Table 2 is fed back to FBIN. The input frequency range for CLKIN is 25 MHz to 50 MHz when using output configuration B. Outputs configured as 1x outputs operate at the CLKIN frequency, while outputs configured as 2x outputs operate at double the frequency of CLKIN. Table 2. Output Configuration B
INPUTS SEL1 L L H H SEL0 L H L H OUTPUTS 1x FREQUENCY All 1Yn 1Yn, 2Yn 1Yn, 2Yn, 3Yn 2x FREQUENCY None 2Yn, 3Yn, 4Yn 3Yn, 4Yn 4Yn
NOTE: n = 1, 2, 3
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CDC586 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS336D FEBRUARY 1993 REVISED OCTOBER 1998
functional block diagram
OE 42 40
CLR FBIN
48
Phase-Lock Loop
CLKIN
45
B2
TEST
41
SEL0
50
One of Four Identical Outputs 1Yn
SEL1 51
Select Logic
One of Four Identical Outputs 2Yn
One of Four Identical Outputs 3Yn
One of Four Identical Outputs 4Yn
4
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ÁÁÁ ÁÁÁ ÁÁÁ
B2
CLR 1Y1 1Y3 2Y1 2Y3 3Y1 3Y3 4Y1 4Y3
ÎÎÎÎÎÎ ÁÁÁÎÎÎÎÎÎ ÁÁÁÁÁÁ ÁÁÁÎÎÎÎÎÎ ÁÁÁÁÁÁ ÁÁÁÎÎÎÎÎÎ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ
CDC586 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS336D FEBRUARY 1993 REVISED OCTOBER 1998
Terminal Functions
TERMINAL NAME NO. I/O DESCRIPTION Clock input. CLKIN is the clock signal distributed by the CDC586 clock-driver circuit. CLKIN provides the reference signal to the integrated PLL that generates the clock output signals. CLKIN must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLKIN signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. CLR is used for testing purposes only. Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to one of the twelve clock outputs to provide frequency and phase lock. The internal PLL adjusts the output clocks to obtain zero phase delay between FBIN and CLKIN. Output enable. OE is the output enable for all outputs. When OE is low, all outputs are enabled. When OE is high, all outputs are in the high-impedance state. Since the feedback signal for the PLL is taken directly from an output terminal, placing the outputs in the high-impedance state interrupts the feedback loop; therefore, when a high-to-low transition occurs at OE, enabling the output buffers, a stabilization time is required before the PLL obtains phase lock. Output configuration select. SEL0 and SEL1 select the output configuration for each output bank (e.g. 1×, 1/2×, or 2×). (see Tables 1 and 2). TEST is used to bypass the PLL circuitry for factory testing of the device. When TEST is low, all outputs operate using the PLL circuitry. When TEST is high, the outputs are placed in a test mode that bypasses the PLL circuitry. TEST should be strapped to GND for normal operation. Output ports. These outputs are configured by SEL1 and SEL0 to transmit one-half or one-fourth the frequency of the VCO. The relationship between the CLKIN frequency and the output frequency is dependent on SEL1 and SEL0 and the frequency of the output being fed back to FBIN. The duty cycle of the Y output signals is nominally 50% independent of the duty cycle of CLKIN. Output ports. 4Y1 4Y3 transmit one-half the frequency of the VCO regardless of the state of SEL1 and SEL0. The relationship between the CLKIN frequency and the output frequency is dependent on the frequency of the output being fed back to FBIN. The duty cycle of the Y output signals is nominally 50% independent of the duty cycle of CLKIN.
CLKIN
45
I
CLR FBIN
40 48
I I
OE
42
I
SEL1, SEL0
51, 50
I
TEST
41
I
1Y1 1Y3 2Y1 2Y3 3Y1 3Y3
2, 5, 8 12, 15, 18 22, 25, 28
O
4Y1 4Y3
32, 35, 38
O
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002.
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