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Part: CDCVF25081PW
Category:
Timing Circuits
-> PLL (Phase locked loop)
-> PLL-Based Clock Buffers (Zero-Delay)
Description: ti CDCVF25081, 1:8 3.3-V Phase Lock Loop Clock Driver
Company: Texas Instruments, Inc.
Datasheet: Download CDCVF25081PW datasheet File size : 1567 kB
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Datasheet text preview:
CDCVF25081 3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A OCTOBER 2001 REVISED FEBRUARY 2003
D Phase-Locked Loop-Based Zero-Delay
Buffer
D Operating Frequency: 8 MHz to 200 MHz D Low Jitter (Cycle-Cycle): ±100 ps Over the D D D D D D D D D
Range 66 MHz to 200 MHz Distributes One Clock Input to Two Banks of Four Outputs Auto Frequency Detection to Disable Device (Power Down Mode) Consumes Less Than 20 µA in Power Down Mode Operates From Single 3.3-V Supply Industrial Temperature Range 40°C to 85°C 25- On-Chip Series Damping Resistors No External RC Network Required Spread Spectrum Clock Compatible (SSC) Available in 16-Pin TSSOP or 16-Pin SOIC Packages
D PACKAGE (SOIC) PW PACKAGE (TSSOP) (TOP VIEW)
CLKIN 1Y0 1Y1 VDD GND 2Y0 2Y1 S2
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
FBIN 1Y3 1Y2 VDD GND 2Y3 2Y2 S1
description
The CDCVF25081 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks to the input clock signal. The CDCVF25081 operates from a nominal supply voltage of 3.3 V. The device also includes integrated series-damping resistors in the output drivers that make it ideal for driving point-to-point loads. Two banks of four outputs each provide low-skew, low-jitter copies of CLKIN. All outputs operate at the same frequency. Output duty cycles are adjusted to 50%, independent of duty cycle at CLKIN. The device automatically goes into power-down mode when no input signal is applied to CLKIN and the outputs go into a low state. Unlike many products containing PLLs, the CDCVF25081 does not require an external RC network. The loop filter for the PLL is included on-chip, minimizing component count, space, and cost. Because it is based on a PLL circuitry, the CDCVF25081 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency signal at CLKIN and any following changes to the PLL reference. The CDCVF25081 is characterized for operation from -40°C to 85°C.
FUNCTION TABLE S2 0 0 1 S1 0 1 0 1Y01Y3 Hi-Z Active Active 2Y02Y3 Hi-Z Hi-Z Active OUTPUT SOURCE N/A. PLL Input clock (PLL bypass) PLL PLL SHUTDOWN Yes No Yes No
1 1 Active Active CLK input frequency < 2 MHz switches the outputs to low level
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
CDCVF25081 3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A OCTOBER 2001 REVISED FEBRUARY 2003
Terminal Functions
TERMINAL NAME 1Y[0:3] 2Y[0:3] CLKIN PIN NO. 2, 3, 14, 15 6, 7, 10, 11 1 TYPE O O I DESCRIPTION Bank 1Yn clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated 25- series-damping resistor. Bank 2Yn clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated 25- series-damping resistor. Clock input. CLKIN provides the clock signal to be distributed by the CDCVF25081 clock driver. CLKIN is used to provide the reference signal to the integrated PLL that generates the output signal. CLKIN must have a fixed frequency and phase in order for the PLL to acquire lock. Once the circuit is powered up and a valid signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to CLKIN. Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be wired to one of the outputs to complete the feedback loop of the internal PLL. The integrated PLL synchronizes the FBIN and output signal so there is nominally zero-delay from input clock to output clock. Ground Select pins to determine mode of operation. See the FUNCTION TABLE for mode selection options. Supply voltage. The supply voltage range is 3 V to 3.6 V
FBIN
16
I
GND S1, S2 VDD
5, 12 9, 8 4, 13
Ground I Power
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CDCVF25081 3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A OCTOBER 2001 REVISED FEBRUARY 2003
functional block diagram
2
25
1Y0
FBIN CLKIN
16 1 PLL M U X 3
25
1Y1
14
25
1Y2
15
25
1Y3
S2
8 Input Select Decoding
S1
9
6
25
2Y0
7
25
2Y1
10
25
2Y2
11
25
2Y3
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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CDCVF25081 3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A OCTOBER 2001 REVISED FEBRUARY 2003
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDD + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous total output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147°C/W D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN Supply voltage, VDD Low level input voltage, VIL High level input voltage, VIH Input voltage, VI High-level output current, IOH Low-level output current, IOL Operating free-air temperature, TA -40 2 0 3.6 12 12 85 3 NOM 3.3 MAX 3.6 0.8 UNIT V V V V mA mA °C
timing requirements over recommended ranges of supply voltage, load and operating free-air temperature
MIN Clock frequency fclk frequency, CL = 25 pF CL = 15 pF 8 66 NOM MAX 100 200 MHz UNIT
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CDCVF25081 3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A OCTOBER 2001 REVISED FEBRUARY 2003
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK II IPD IOZ CI CI CO VOH Input voltage Input current Power down current Output 3-state Input capacitance at FBIN, CLKIN Input capacitance at S1, S2 Output capacitance TEST CONDITIONS VDD = 3 V, VI = 0 V or VDD fCLKIN = 0 MHz, Vo = 0 V or VDD, VI = 0 V or VDD VI = 0 V or VDD VI = 0 V or VDD VDD = min to max, VDD = 3 V, VDD = 3 V, VDD = min to max, VDD = 3 V, VDD = 3 V, VDD = 3 V, IOH High-level out ut current output VDD = 3.3 V, VDD = 3.6 V, VDD = 3 V, VDD = 3.3 V, VDD = 3.6 V, All typical values are at respective nominal VDD. For IDD over frequency see Figure 7. IOH = -100 µA IOH = -12 mA IOH = -6 mA IOL = 100 µA IOL = 12 mA IOL = 6 mA VO = 1 V VO = 1.65 V VO = 3.135 V VO = 1.95 V VO = 1.65 V VO = 0.4 V 24 30 -15 26 33 14 mA mA VDD 0.2 2.1 2.4 0.2 0.8 0.55 V II = -18 mA VDD = 3.3 V VDD = 3.6 V 4 2.2 3 MIN TYP MAX 1.2 ±5 20 ±5 UNIT V µA µA µA pF pF pF
High-level out ut voltage output
V
VOL
Low-level out ut voltage output
IOL
Low-level output current
POST OFFICE BOX 655303
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