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Part: CDCVF2509
Category:
Timing Circuits
-> Clock Distribution
-> General Purpose/
Description: 3.3v Phase-lock Loop Clock Driver
Company: Texas Instruments, Inc.
Datasheet: Download CDCVF2509 datasheet File size : 1567 kB
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Datasheet text preview:
CDCVF2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS637B DECEMBER 1999 REVISED JULY 2001
D D D D D D D D D D D D D D
Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1 Spread Spectrum Clock Compatible Operating Frequency 50 MHz to 175 MHz Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps Jitter (cyc cyc) at 66 MHz to 166 MHz Is |70| ps Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices Available in Plastic 24-Pin TSSOP Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input 25- On-Chip Series Damping Resistors No External RC Network Required Operates at 3.3 V
PW PACKAGE (TOP VIEW)
AGND VCC 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 VCC 1G FBOUT
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
CLK AVCC VCC 2Y0 2Y1 GND GND 2Y2 2Y3 VCC 2G FBIN
description
The CDCVF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2509 operates at a 3.3-V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDCVF2509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDCVF2509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. The CDCVF2509 is characterized for operation from 0°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2001, Texas Instruments Incorporated
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CDCVF2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS637B DECEMBER 1999 REVISED JULY 2001
description (continued)
For application information refer to application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) (literature number SCAA039).
FUNCTION TABLE INPUTS 1G X L L H H 2G X L H L H CLK L H H H H 1Y (0:4) L L L H H OUTPUTS 2Y (0:3) L L H L H FBOUT L H H H H
functional block diagram
1G 11
3
1Y0
4
1Y1
5
1Y2
8
1Y3
9 14
1Y4
2G
21
2Y0
20
2Y1
CLK
24
FBIN
13
AVCC
23
2
ÎÎÎÎÎÎÎ ÎÁÁÁÁÁÎ ÎÎÎÎÎÁ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
PLL
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17
2Y2
16
2Y3
12
FBOUT
· DALLAS, TEXAS 75265
CDCVF2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS637B DECEMBER 1999 REVISED JULY 2001
AVAILABLE OPTIONS PACKAGE TA 0°C to 85°C to 85°C SMALL OUTLINE (PW) CDCVF2509PWR CDCVF2509PW
Terminal Functions
TERMINAL NAME NO. TYPE DESCRIPTION Clock input. CLK provides the clock signal to be distributed by the CDCVF2509 clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4) are disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same frequency as CLK. Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same frequency as CLK. Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an integrated 25- series-damping resistor. Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via the 1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control input. Each output has an integrated 25- series-damping resistor. Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via the 2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control input. Each output has an integrated 25- series-damping resistor. Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. Analog ground. AGND provides the ground reference for the analog circuitry. Power supply Ground
CLK
24
I
FBIN
13
I
1G
11
I
2G
14
I
FBOUT
12
O
1Y (0:4)
3, 4, 5, 8, 9
O
2Y (0:3)
21, 20, 17, 16
O
AVCC AGND VCC GND
23 1 2, 10, 15, 22 6, 7, 18, 19
Power Ground Power Ground
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CDCVF2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS637B DECEMBER 1999 REVISED JULY 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, AVCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVCC VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. AVCC must not exceed VCC+ 0.7 V 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This value is limited to 4.6 V maximum. 4. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002. DISSIPATION RATING TABLE PACKAGE PW BOARD TYPE JEDEC low-K JEDEC high-K RJA 114.5°C/W 62.1°C/W TA 25°C POWER RATING 920 mW 1690 mW DERATING FACTOR§ ABOVE TA = 25°C 8.7 mW/°C 16.1 mW/°C TA = 70°C POWER RATING 520 mW 960 mW TA = 85°C POWER RATING 390 mW 720 mW
JECEC high-K board has better thermal performance due to multiple internal copper planes. § This is the inverse of the traditional junction-to-ambient thermal resistance (RJA).
recommended operating conditions (see Note 5)
MIN Supply voltage, VCC, AVCC High-level input voltage, VIH Low-level input voltage, VIL Input voltage, VI High-level output current, IOH Low-level output current, IOL Operating free-air temperature ,TA NOTE 5: Unused inputs must be held high or low to prevent them from floating. 0 0 3 2 0.8 VCC 12 12 85 MAX 3.6 UNIT V V V V mA mA °C
timing requirements over recommended ranges of supply voltage and operating free-air temperature
MIN fclk Clock frequency Input clock duty cycle Stabilization time¶ 50 40% MAX 175 60% UNIT MHz
1 ms Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application.
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CDCVF2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS637B DECEMBER 1999 REVISED JULY 2001
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH Input clamp voltage High-level output voltage TEST CONDITIONS II = 18 mA IOH = 100 µA IOH = 12 mA IOH = 6 mA IOL = 100 µA IOL = 12 mA IOL = 6 mA VO = 1 V VO = 1.65 V VO = 3.135 V VO = 1.95 V VO = 1.65 V VO = 0.4 V VI = VCC or GND VI = VCC or GND, Outputs: low or high IO = 0, VCC, AVCC 3V MIN to MAX 3V 3V MIN to MAX 3V 3V 3V 3.3 V 3.6 V 3V 3.3 V 3.6 V 3.6 V 3.6 V, 0 V 3.3 V to 3.6 V 3.3 V 2.5 30 40 10 ±5 40 500 µA µA µA pF pF mA 28 36 8 mA MIN VCC0.2 2.1 2.4 0.2 0.8 0.55 V TYP MAX 1.2 UNIT V V
VOL
Low-level output voltage
IOH
High-level output current
IOL II ICC ICC Ci
Low-level output current Input current Supply current (static, output not switching) Change in supply current Input capacitance
One input at VCC 0.6 V, Other inputs at VCC or GND VI = VCC or GND VO = VCC or GND
Co Output capacitance 3.3 V 2.8 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. For dynamic ICC vs Frequency, refer to Figures 8 and 9.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF (see Note 6 and Figures 1 and 2)
PARAMETER Phase error time static (normalized) (see Figures 36) tsk(o) Output skew time Phase error time jitter (see Note 7) Jitter(cycle-cycle) (see Figure 7) Duty cycle tr tf tPLH(bypass mode) tPHL(bypass mode) Rise time Fall time Low-to-high propagation delay time, bypass mode High-to-low propagation delay time, bypass mode FROM (INPUT) CLK = 66 MHz to166 MHz Any Y CLK = 66 MHz to 100 MHz CLK = 100 MHz to 166 MHz f(CLK) > 60 MHz VO = 0.4 V to 2 V VO = 2 V to 0.4 V CLK CLK TO (OUTPUT) FBIN Any Y Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT 45% 0.3 0.3 1.8 1.8 50 |70| |65| 55% 1.1 1.1 3.9 3.9 ns/V ns/V ns ns VCC, AVCC = 3.3 V ± 0.3 V MIN 125 TYP MAX 125 100 50 ps ps ps UNIT
These parameters are not production tested. The tsk(o) specification is only valid for equal loading of all outputs. NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 7. Calculated per PC DRAM SPEC (tphase error, static jitter(cycle-to-cycle)).
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