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Part: CY74FCT841TSOIC
Category:
Description: 10-bit Latch
Company: Texas Instruments, Inc.
Datasheet: Download CY74FCT841TSOIC datasheet File size : 207 kB
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Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered.
CY54/74FCT841T
SCCS035 - September 1994 - Revised March 2000
10-Bit Latch
· High-speed parallel latches · Buffered common latch enable input
Features
· Function, pinout, and drive compatible with FCT, F, and AM29841 logic · FCT-C speed at 5.5 ns max. (Com'l) FCT-B speed at 6.5 ns max. (Com'l) · Reduced VOH (typically = 3.3V) versions of equivalent FCT functions · Edge-rate control circuitry for significantly improved noise characteristics · Power-off disable feature · Matched rise and fall times · ESD > 2000V · Fully compatible with TTL input and output logic levels · Sink current 64 mA (Com'l), 32 mA (Mil) Source current 32 mA (Com'l), 12 mA (Mil)
Functional Description
The FCT841T bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carr ying parity. The FCT841T is a buffered 10-bit wide version of the FCT373 function. The FCT841T high-performance interface is designed for high-capacitance load drive capability while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high impedance state and are designed with a power-off disable feature to allow for live insertion of boards.
Functional Block Diagram
D0 D1 D2 D3 D4 D5 D N- 1 DN
D LE Q
D LE
Q Q
D LE
Q Q
D LE
Q Q
D LE
Q Q
D LE
Q Q
D LE
Q Q
D LE
Q Q
LE
OE Y0 Y1 Y2 Y3 Y4 Y5 YN- 1 YN
Logic Block Diagram
D 10 D LE LE OE Q 10
Pin Configurations
DIP/QSOP/SOIC Top View
Y OE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 LE
Copyright
© 2000, Texas Instruments Incorporated
CY54/74FCT841T
Pin Description
Name D LE Y OE I I O I I/O The latch data inputs. The latch enable input. The latches are transparent when LE is HIGH. Input data is latched on the HIGH-to-LOW transition. The three-state latch outputs. The output enable control. When the OE is LOW, the outputs are enabled. When OE is HIGH, the outputs Y1 are in the high impedance (off) state. Description
Function Table[1]
Inputs OE H H H H L L L LE X H H L H H L D X L H X L H X Internal Outputs O X L H NC L H NC Y Z Z Z Z L H NC Function High Z
Latched (High Z) Transparent Latched
Maximum Ratings[2, 3]
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ......... 65°C to +150°C Ambient Temperature with Power Applied ............ 65°C to +135°C Supply Voltage to Ground Potential ...... 0.5V to +7.0V DC Input Voltage........... 0.5V to +7.0V DC Output Voltage ........ 0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin) ...... 120 mA Power Dissipation .......... 0.5W Static Discharge Voltage...........>2001V (per MIL-STD-883, Method 3015)
Operating Range
Range Commercial Military[4] Range All All Ambient Temperature 40°C to +85°C 55°C to +125°C VCC 5V ± 5% 5V ± 10%
Notes: 1. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don't Care, NC = No Change, Z = High Impedance. 2. Unless otherwise noted, these limits are over the operating free-air temperature range. 3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. 4. TA is the "instant on" case temperature.
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CY54/74FCT841T
Electrical Characteristics Over the Operating Range
Parameter VOH Description Output HIGH Voltage Test Conditions VCC= Min., IOH = -32 mA VCC= Min., IOH = -15 mA VCC= Min., IOH = -12 mA VOL VIH VIL VH VIK II IIH IIL IOZH IOZL IOS IOFF Output LOW Voltage Input HIGH Voltage Input LOW Voltage Hysteresis
[6]
Min. Com'l Com'l Mil Com'l Mil 2.0 2.0 2.4 2.4
Typ.[5] 3.3 3.3 0.3 0.3
Max.
Unit V V V
VCC= Min., IOL = 64 mA VCC= Min., IOL = 32 mA
0.55 0.55 0.8
V V V V V V µA µA µA µA µA mA µA
All inputs VCC= Min., IIN= -18 mA VCC= Max., VIN= VCC VCC= Max., VIN= 2.7V VCC= Max., VIN= 0.5V VCC = Max., VOUT = 2.7V VCC = Max., VOUT = 0.5V VCC = Max., VOUT = 0.0V VCC = 0V, VOUT = 4.5V -60
0.2 -0.7 -1.2 5 ±1 ±1 10 -10 -120 -225 ±1
Input Clamp Diode Voltage Input HIGH Current Input HIGH Current Input LOW Current Off State HIGH-Level Output Current Off State LOW-Level Output Current Output Short Circuit Current[7] Power-Off Disable
Capacitance[6]
Parameter CIN COUT Input Capacitance Output Capacitance Description Typ.[5] 5 9 Max. 10 12 Unit pF pF
Notes: 5. Typical values are at VCC=5.0V, TA=+25°C ambient. 6. This parameter is specified but not tested. 7. Not more than one output should be shor ted at a time. Duration of shor t should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shor ting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last.
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CY54/74FCT841T
Power Supply Characteristics
Parameter ICC ICC ICCD Description Quiescent Power Supply Current (TTL inputs HIGH) Test Conditions VCC = Max., VIN = 3.4V, f1 = 0, Outputs Open[8] Typ.[5] 0.1 0.5 0.06 Max. 0.2 2.0 0.12 Unit mA mA mA/MHz Quiescent Power Supply Current VCC = Max., VIN 0.2V, VIN VCC-0.2V
Dynamic Power Supply Current[9] VCC = Max., 50% Duty Cycle, Outputs Open, One Input Toggling, OE =GND, LE = VCC, VIN 0.2V or VIN VCC-0.2V Total Power Supply Current[10] VCC=Max., 50% Duty Cycle, Outputs Open, One Bit Toggling at f1=10 MHz, OE = GND, LE = VCC, VIN 0.2V or VIN VCC-0.2V VCC = Max., 50% Duty Cycle, Outputs Open, One Bit Toggling at f1 =10 MHz, OE = GND, LE = VCC, VIN = 3.4V or VIN = GND VCC = Max., 50% Duty Cycle, Outputs Open, Ten Bits Toggling at f1 = 2.5 MHz, OE =GND, LE = VCC, VIN 0.2V or VIN VCC-0.2V VCC=Max., 50% Duty Cycle, Outputs Open, Ten Bits Toggling at f1 = 2.5 MHz, OE = GND, LE = VCC, VIN = 3.4V or VIN = GND
IC
0.7
1.4
mA
1.0
2.4
mA
1.0
3.2[11]
mA
4.1
13.2[11]
mA
Notes: 8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND. 9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. = IQUIESCENT + IINPUTS + IDYNAMIC 10. IC IC = ICC+ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) DH = Duty Cycle for TTL inputs HIGH NT = Number of TTL inputs at DH ICCD = Dynamic Current caused by an input transition pair HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 N1 = Number of inputs changing at f1 All currents are in milliamps and all frequencies are in megahertz. 11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
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CY54/74FCT841T
Switching Characteristics Over the Operating Range[12]
FCT841AT Military Parameter tPLH tPHL Description Propagation Delay D1 to Y1 (L =HIGH) Propagation Delay D1 to Y1 (LE=HIGH) tSU tH tPLH tPHL Data to LE Set-Up Time Data to LE Hold Time Propagation Delay LE to Y1 Propagation Delay LE to Y1 [12] tW tPZH tPZL Test Load CL = 50 pF RL = 500 CL = 300 pF RL = 500 CL = 50 pF RL = 500 CL = 50 pF RL = 500 CL = 50 pF RL = 500 CL = 300 pF RL = 500 Min. 1.5 1.5 2.5 3.0 1.5 1.5 5.0 1.5 1.5 1.5 1.5 13.0 25.0 9.0 10.0 13.0 20.0 Max. 10.0 15.0 Commercial Min. 1.5 1.5 2.5 2.5 1.5 1.5 4.0 1.5 1.5 1.5 1.5 11.5 23.0 7.0 8.0 12.0 16.0 Max. 9.0 13.0 FCT841BT Commercial Min. 1.5 1.5 2.5 2.5 1.5 1.5 4.0 1.5 1.5 1.5 1.5 8.0 14.0 6.0 7.0 8.0 15.5 Max. 6.5 13.0 FCT841CT Commercial Min. 1.5 1.5 2.5 2.5 1.5 1.5 4.0 1.5 1.5 1.5 1.5 6.5 12.0 5.7 6.0 6.4 15.0 5.5 13.0 Fig. Max. Unit No.[13] ns ns ns ns ns ns ns ns ns ns ns 1, 3 1, 3 9 9 1, 3 1, 3 5 1, 7, 8 1, 7, 8 1, 7, 8 1, 7, 8
LE Pulse Width (HIGH) CL = 50 pF RL = 500 Output Enable Time OE to Y1 Output Enable Time OE to Y1[12] CL = 50 pF RL = 500 CL = 300 pF RL = 500 CL = 5 pF RL = 500 CL = 50 pF RL = 500
tPHZ tPLZ
Output Disable Time OE to Y1[12] Output Disable Time OE to Y1
Ordering Information
Speed (ns) 5.5 6.5 9.0 10.0 Ordering Code CY74FCT841CTQCT CY74FCT841CTSOC/SOCT CY74FCT841BTPC CY74FCT841ATSOC/SOCT CY54FCT841ATDMB Package Name Q13 S13 P13/P13A S13 D14 Package Type 24-Lead (150-Mil) QSOP 24-Lead (300-Mil) Molded SOIC 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) Molded SOIC 24-Lead (300-Mil) CerDIP Commercial Commercial Military Operating Range Commercial
Notes: 12. Minimum limits are specified but not tested on Propagation Delays. 13. See "Parameter Measurement Information" in the General Information section.
Document #: 38-00273-B
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