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Details, datasheet, quote on part number:DAC900U
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| Part: | DAC900U |
| Category: | Data Conversion => DAC (Digital to Analog Converters) |
| Description: | ti DAC900, 10-Bit, 165MSPS SpeedPlus(TM) DAC Scalable Current Outputs Between 2mA to 20mA |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download DAC900U datasheet File size : 491 kB |
| Request For quote: | Find where to buy DAC900U
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Datasheet text preview:
DAC900
DAC 900
DAC9 00
SBAS093B MAY 2002
10-Bit, 165MSPS DIGITAL-TO-ANALOG CONVERTER
TM
FEATURES
q q q q q SINGLE +5V OR +3V OPERATION HIGH SFDR: 5MHz Output at 100MSPS: 68dBc LOW GLITCH: 3pV-s LOW POWER: 170mW at +5V INTERNAL REFERENCE: Optional Ext. Reference Adjustable Full-Scale Range Multiplying Option
DESCRIPTION
The DAC900 is a high-speed, Digital-to-Analog Converter (DAC) offering a 10-bit resolution option within the SpeedPlus family of high-performance converters. Featuring pin compatibility among family members, the DAC908, DAC902, and DAC904 provide a component selection option to an 8-, 12-, and 14-bit resolution, respectively. All models within this family of DACs support update rates in excess of 165MSPS with excellent dynamic performance, and are especially suited to fulfill the demands of a variety of applications. The advanced segmentation architecture of the DAC900 is optimized to provide a high Spurious-Free Dynamic Range (SFDR) for single-tone, as well as for multi-tone signals--essential when used for the transmit signal path of communication systems. The DAC900 has a high impedance (200k) current output with a nominal range of 20mA and an output compliance of up to 1.25V. The differential outputs allow for both a differential or singleended analog signal interface. The close matching of the current outputs ensures superior dynamic performance in the differential configuration, which can be implemented with a transformer. Utilizing a small geometry CMOS process, the monolithic DAC900 can be operated on a wide, single-supply range of +2.7V to +5.5V. Its low power consumption allows for use in portable and batteryoperated systems. Further optimization can be realized by lowering the output current with the adjustable full-scale option. For noncontinuous operation of the DAC900, a power-down mode results in only 45mW of standby power. The DAC900 comes with an integrated 1.24V bandgap reference and edge-triggered input latches, offering a complete converter solution. Both +3V and +5V CMOS logic families can be interfaced to the DAC900. The reference structure of the DAC900 allows for additional flexibility by utilizing the on-chip reference, or applying an external reference. The full-scale output current can be adjusted over a span of 2mA to 20mA, with one external resistor, while maintaining the specified dynamic performance. The DAC900 is available in SO-28 and TSSOP-28 packages.
APPLICATIONS
q COMMUNICATION TRANSMIT CHANNELS WLL, Cellular Base Station Digital Microwave Links Cable Modems q WAVEFORM GENERATION Direct Digital Synthesis (DDS) Arbitrary Waveform Generation (ARB) q MEDICAL/ULTRASOUND q HIGH-SPEED INSTRUMENTATION AND CONTROL q VIDEO, DIGITAL TV
+VA DAC900 LSB Switches Segmented Switches IOUT IOUT BYP BW +VD
FSA REFIN
Current Sources
INT/EXT Latches +1.24V Ref. 10-Bit Data Input AGND CLK D9...D0 DGND PD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2002, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS
+VA to AGND ...... 0.3V to +6V +VD to DGND ...... 0.3V to +6V AGND to DGND ........ 0.3V to +0.3V +VA to +VD ....... 6V to +6V CLK, PD to DGND ..... 0.3V to VD + 0.3V D0-D9 to DGND ......... 0.3V to VD + 0.3V IOUT, IOUT to AGND ........ 1V to VA + 0.3V BW, BYP to AGND ..... 0.3V to VA + 0.3V REFIN, FSA to AGND ....... 0.3V to VA + 0.3V INT/EXT to AGND ...... 0.3V to VA + 0.3V Junction Temperature ........... +150°C Case Temperature ....... +100°C Storage Temperature ........... +125°C
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE /ORDERING INFORMATION
PACKAGE DRAWING NUMBER 217 SPECIFIED TEMPERATURE RANGE 40°C to +85°C PACKAGE MARKING DAC900U ORDERING NUMBER(1) DAC900U DAC900U/1K DAC900E DAC900E/2K5 TRANSPORT MEDIA Rails Tape and Reel Rails Tape and Reel
PRODUCT DAC900U
PACKAGE SO-28
"
DAC900E
"
TSSOP-28
"
360
"
40°C to +85°C
"
DAC900E
"
"
"
"
"
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of "DAC900E/2K5" will get a single 2500-piece Tape and Reel.
DEMO BOARD ORDERING INFORMATION
PRODUCT DAC900U DAC900E DEMO BOARD ORDERING NUMBER DEM-DAC90xU DEM-DAC900E COMMENT Populated evaluation board without DAC. Order sample of desired DAC90x model separately. Populated evaluation board including the DAC900E.
ELECTRICAL CHARACTERISTICS
At TA = full specified temperature range, +VA = +5V, +VD = +5V, differential transformer coupled output, 50ý doubly terminated, unless otherwise specified. DAC900U/E PARAMETER RESOLUTION OUTPUT UPDATE RATE Output Update Rate (fCLOCK) Full Specified Temperature Range, Operating STATIC ACCURACY(1) Differential Nonlinearity (DNL) Integral Nonlinearity (INL) DYNAMIC PERFORMANCE Spurious-Free Dynamic Range (SFDR) fOUT = 1.0MHz, fCLOCK = 25MSPS fOUT = 2.1MHz, fCLOCK = 50MSPS fOUT = 5.04MHz, fCLOCK = 50MSPS fOUT = 5.04MHz, fCLOCK = 100MSPS fOUT = 20.2MHz, fCLOCK = 100MSPS fOUT = 25.3MHz, fCLOCK = 125MSPS fOUT = 41.5MHz, fCLOCK = 125MSPS fOUT = 27.4MHz, fCLOCK = 165MSPS fOUT = 54.8MHz, fCLOCK = 165MSPS Spurious-Free Dynamic Range within a Window fOUT = 5.04MHz, fCLOCK = 50MSPS fOUT = 5.04MHz, fCLOCK = 100MSPS Total Harmonic Distortion (THD) fOUT = 2.1MHz, fCLOCK = 50MSPS fOUT = 2.1MHz, fCLOCK = 125MSPS Two Tone fOUT1 = 13.5MHz, fOUT2 = 14.5MHz, fCLOCK = 100MSPS Output Settling Time(2) fCLOCK 2.7V to 3.3V 4.5V to 5.5V Ambient, T A TA = +25°C = 25MSPS, fOUT = 1.0MHz TA = +25°C To Nyquist 70 76 75 68 68 62 62 53 59 53 78 78 74 73 60 30 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc ns 125 165 40 0.5 1.0 CONDITIONS MIN TYP 10 165 200 +85 ±0.3 ±0.5 +0.5 +1.0 MAX UNITS Bits MSPS MSPS °C LSB LSB
2MHz Span 4MHz Span
to 0.1%
2
DAC900
SBAS093B
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = +25°C, +VA = +5V, +VD = +5V, differential transformer coupled output, 50 doubly terminated, unless otherwise specified. DAC900U/E PARAMETER DYNAMIC PERFORMANCE (Cont.) Output Rise Time(2) Output Fall Time(2) Glitch Impulse DC-ACCURACY Full-Scale Output Range(3)(FSR) Output Compliance Range Gain Error Gain Error Gain Drift Offset Error Offset Drift Power-Supply Rejection, +VA Power-Supply Rejection, +VD Output Noise Output Resistance Output Capacitance REFERENCE Reference Voltage Reference Tolerance Reference Voltage Drift Reference Output Current Reference Input Resistance Reference Input Compliance Range Reference Small-Signal Bandwidth(4) DIGITAL INPUTS Logic Coding Latch Command Logic High Voltage, VIH Logic Low Voltage, VIL Logic High Voltage, VIH Logic Low Voltage, VIL Logic High Current, IIH(5) Logic Low Current, IIL Input Capacitance POWER SUPPLY Supply Voltages + VA +VD Supply Current(6) IVA IVA, Power-Down Mode IVD Power Dissipation Power Dissipation, Power-Down Mode Thermal Resistance, JA SO-28 TSSOP-28 CONDITIONS MIN TYP MAX UNITS
10% to 90% 10% to 90%
2 2 3 2.0 1.0 10 10 0.025 ±0.1 0.2 0.025 +0.2 +0.025 50 200 12 +1.24 ±10 ±50 10 1 0.1 1.3 Straight Binary Rising Edge of Clock 5 0 3 0 ±20 ±20 5 1.25 20.0 +1.25 +10 +10 +0.025
ns ns pV-s mA V %FSR %FSR p p m F S R /° C %FSR ppmFSR/°C %FSR/V %FSR/V pA/ Hz k pF V % p p m F S R /° C µA M V MHz
All Bits High, IOUT With Internal Reference With External Reference With Internal Reference With Internal Reference With Internal Reference
±1 ±2 ±120
IOUT = 20mA, RLOAD = 50 IOUT, IOUT to Ground
+ VD + VD + VD + VD + VD + VD
= = = = = =
+5V +5V +3V +3V +5V +5V
3.5 2
1.2 0.8
V V V V µA µA pF
+2.7 +2.7
+5 +5 24 1.1 8 170 50 45 75 50
+5.5 +5.5 30 2 15 230
V V mA mA mA mW mW mW °C/W °C/W
+5V, IOUT = 20mA +3V, IOUT = 2mA
NOTES: (1) At output IOUT, while driving a virtual ground. (2) Measured single-ended into 50 Load. (3) Nominal full-scale output current is 32x IREF; see Application Section for details. (4) Reference bandwidth depends on size of external capacitor at the BW pin and signal level. (5) Typically 45µA for the PD pin, which has an internal pull-down resistor. (6) Measured at fCLOCK = 50MSPS and fOUT = 1.0MHz.
DAC900
SBAS093B
3
PIN CONFIGURATION
Top View SO, TSSOP
PIN DESCRIPTIONS
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DESIGNATOR Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 NC NC NC NC PD DESCRIPTION Data Bit 1 (D9), MSB Data Bit 2 (D8) Data Bit 3 (D7) Data Bit 4 (D6) Data Bit 5 (D5) Data Bit 6 (D4) Data Bit 7 (D3) Data Bit 8 (D2) Data Bit 9 (D1) Data Bit 10 (D0), LSB No Connection No Connection No Connection No Connection Power Down, Control Input; Active HIGH. Contains internal pull-down circuit; may be left unconnected if not used. Reference Select Pin; Internal ( = 0) or External ( = 1) Reference Operation. Reference Input/Ouput. See Applications section for further details. Full-Scale Output Adjust Bandwidth/Noise Reduction Pin: Bypass with 0.1µF to +VA for Optimum Performance. Analog Ground Complementary DAC Current Output DAC Current Output Bypass Node: Use 0.1µF to AGND Analog Supply Voltage, 2.7V to 5.5V No Connection Digital Ground Digital Supply Voltage, 2.7V to 5.5V Clock Input
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9
1 2 3 4 5 6 7 DAC900 8 9
28 27 26 25 24 23 22 21 20 19 18 17 16 15
CLK +VD DGND NC +VA BYP IOUT IOUT AGND BW FSA REFIN INT/EXT PD
16 17 18 19
INT/EXT REFIN FSA BW
Bit 10 10 NC 11 NC 12 NC 13 NC 14
20 21 22 23 24 25 26 27 28
AGND IOUT IOUT BYP +VA NC DGND +VD CLK
TYPICAL CONNECTION CIRCUIT
+5V 0.1µF +VA DAC900 FSA REFIN RSET 0.1µF Current Sources LSB Switches Segmented MSB Switches BW +VD IOUT IOUT BYP 0.1µF 50 20pF 50 1:1 +5V
20pF
INT/EXT PD Latches +1.24V Ref. 10-Bit Data Input AGND CLK D9.......D0 DGND
4
DAC900
SBAS093B
TIMING DIAGRAM
t2 CLOCK tS D13 D0 Data Changes tH Stable Valid Data Data Changes tPD tSET t1
Iout or Iout
SYMBOL t1 t2 tS tH t PD tSET
DESCRIPTION Clock Pulse HIGH Time Clock Pulse LOW Time Data Setup Time Data Hold Time Propagation Delay Time Output Settling Time to 0.1%
MIN
TYP 3 3 1.5 1.0 1 30
MAX
UNITS ns ns ns ns ns ns
DAC900
SBAS093B
5
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