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Part: GC2011A
Category:
Description:
Company: Texas Instruments, Inc.
Datasheet: Download GC2011A datasheet File size : 814 kB
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SLWS129A
GC2011A
3.3V DIGITAL FILTER CHIP
DATASHEET
March 21, 2000
Information provided by Graychip is believed to be accurate and reliable. No responsibility is assumed by Graychip for its use, nor for any infringement of patents or other rights of third parties which may arise from its use. No license is granted by implication or otherwise under any patent rights of Graychip.
GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
REVISION HISTORY
Revision
0.0 1.0
Date
3 Feb 1999 22 Sept, 1999 Original
Description
Preliminary markings removed Section 7: Electrical and timing tables changed to reflect production test Pg 19, Sec 3.7, Table 8, changed Hilbert Transform output register to 2000 Pg 25: added ball grid array package Pg 33: changed the gain equation to reference the MSBs of the input and output. Page 25, Rotated marking text on PBGA package Page 35, Snap rate of 2 is invalid Page 39, Changed test load to +/- 2mA from 4mA Page 40, Changed Output delay threshold (Note 4) to 1.3v. Page 40, Changed Data to output MIN delay to 1ns to match test.
1.1
21 Mar 2000
Texas Instruments Incorporated
-i-
This document contains information which may be changed at any time without notice
GC2011A 3.3V DIGITAL FILTER CHIP
1.0
1.1 1.2 1.3
SLWS129A
KEY FEATURES ....... 1
BLOCK DIAGRAM ..............1 GC2011A TO GC2011 COMPARISON....... 2 DATASHEET OVERVIEW ...........3
2.0
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14
FUNCTIONAL DESCRIPTION ......... 4
TRANSVERSAL FILTERS ...........5 CONTROL INTERFACE ..... 6 COUNTER AND SYNCHRONIZATION CIRCUIT......... 7 INPUT MUX ..........8 INPUT NEGATION ..............8 A/B FILTER PATHS ............8 FILTER CELL .......9 ACCUMULATOR ......10 24 BIT MUX CIRCUIT .......10 SUMMER ...........10 OUTPUT NEGATION ........11 GAIN ..........11 OUTPUT MUX ....11 SNAPSHOT MEMORY .....11
3.0
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10
FILTERING MODES ........13
FULL RATE ........14 HALF RATE ........15 QUARTER RATE ..............16 DOUBLE RATE I/O ...........16 DECIMATION .....17 INTERPOLATION .............18 HILBERT TRANSFORM FILTERS ............19 REAL TO COMPLEX QUADRATURE DOWN CONVERT ........20 COMPLEX TO REAL QUADRATURE UPCONVERT .......21 DIAGNOSTICS ...22
4.0
4.1 4.2
PACKAGING ..........23
160 PIN QUAD FLAT PACK (QFP) PACKAGE ..........23 160 PIN BALL GRID ARRAY (PBGA) PACKAGE........25
5.0 6.0
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10
PIN DESCRIPTIONS .......27 CONTROL REGISTERS ..28
A-PATH AND B-PATH CONTROL REGISTER 0 ........29 A-PATH AND B-PATH CONTROL REGISTER 1 ........31 CASCADE MODE CONTROL REGISTER ........32 COUNTER REGISTER .....32 GAIN REGISTER ..............32 OUTPUT MODE REGISTER ......34 SNAPSHOT MODE CONTROL REGISTERS ....35 SNAPSHOT START CONTROL REGISTER .....36 ONE SHOT ADDRESS .....36 NEW MODES REGISTER .........37
7.0
7.1 7.2 7.3 7.4 7.5
SPECIFICATIONS ...........38
ABSOLUTE MAXIMUM RATINGS ............38 RECOMMENDED OPERATING CONDITIONS ..........38 THERMAL CHARACTERISTICS ........38 DC CHARACTERISTICS ...........39 AC CHARACTERISTICS ...........40
8.0
8.1 8.2 8.3 8.4 8.5
APPLICATION NOTES ....41
POWER AND GROUND CONNECTIONS .........41 STATIC SENSITIVE DEVICE ....41 100 MHZ OPERATION .....41 REDUCED VOLTAGE OPERATION .........41 SYNCHRONIZING MULTIPLE GC2011A CHIPS .......42
Texas Instruments Incorporated
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This document contains information which may be changed at any time without notice
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