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Part: IVC102U
Category: Analog & Mixed-Signal Processing -> Amplifiers -> Switched Integration Amplifiers
Description: ti IVC102, Precision Switched Integrator Transimpedance Amplifier
Company: Texas Instruments, Inc.
Datasheet: Download IVC102U datasheet File size : 54 kB
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Datasheet text preview:
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IVC102
PRECISION SWITCHED INTEGRATOR TRANSIMPEDANCE AMPLIFIER
APPLICATIONS
q PRECISION LOW CURRENT MEASUREMENT q PHOTODIODE MEASUREMENTS q IONIZATION CHAMBER MEASUREMENTS q CURRENT/CHARGE-OUTPUT SENSORS q LEAKAGE CURRENT MEASUREMENT
DESCRIPTION
The IVC102 is a precision integrating amplifier with FET op amp, integrating capacitors, and low leakage FET switches. It integrates low-level input current for a user-determined period, storing the resulting voltage on the integrating capacitor. The output voltage can be held for accurate measurement. The IVC102 provides a precision, lower noise alternative to conventional transimpedance op amp circuits that require a very high value feedback resistor. The IVC102 is ideal for amplifying low-level sensor currents from photodiodes and ionization chambers. The input signal current can be positive or negative. TTL/CMOS-compatible timing inputs control the integration period, hold and reset functions to set the effective transimpedance gain and to reset (discharge) the integrator capacitor. Package options include 14-Pin plastic DIP and SO-14 surface-mount packages. Both are specified for the 40°C to 85°C industrial temperature range.
V+
FEATURES
q ON-CHIP INTEGRATING CAPACITORS q GAIN PROGRAMMED BY TIMING q LOW INPUT BIAS CURRENT: 750fA max q LOW NOISE q LOW SWITCH CHARGE INJECTION q FAST PULSE INTEGRATION q LOW NONLINEARITY: 0.005% typ q 14-PIN DIP, SO-14 SURFACE MOUNT
6 VB 5 ICnization o hamber IIN 4 3 2 S1 1 C1 C2
C3 30pF
60pF
14
V
O
=
1 I (t) dt CINT IN
10pF S2 10 VO
0V
Positive or Negative Signal Integration
Hold
Integrate
Hold
Reset
9 Photodiode Gnalog A round 11 S1 12 S2 13 V
S1 S2
Logic Low closes switches
G igital D round
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© 1996 Burr-Brown Corporation
PDS-1329A 1
IVC102 June, 1996 Printed in U.S.A.
SBFS009
SPECIFICATIONS
At TA = +25°C, VS = ±15V, RL = 2k, C INT = C1 + C2 + C3 , 1ms integration period(1), unless otherwise specified. IVC102P, U PARAMETER TRANSFER FUNCTION Gain Error vs Temperature Nonlinearity Input Current Range Offset Voltage(2) vs Temperature vs Power Supply Droop Rate, Hold Mode OP AMP Input Bias Current vs Temperature Offset Voltage (Op Amp VOS) vs Temperature vs Power Supply Noise Voltage INTEGRATION CAPACITORS C1 + C2 + C3 vs Temperature C1 C2 C3 OUTPUT Voltage Range, Positive Negative Short-Circuit Current Capacitive Load Drive Noise Voltage DYNAMIC CHARACTERISTIC Op Amp Gain-Bandwidth Op Amp Slew Rate Reset Slew Rate Settling Time, 0.01% DIGITAL INPUTS VIH (referred to digital ground) VIL (referred to digital ground) IIH IIL Switching Time POWER SUPPLY Voltage Range: Positive Negative Current: Positive Negative Analog Ground Digital Ground TEMPERATURE RANGE Operating Range Storage Thermal Resistance, JA DIP SO-14 RL = 2k RL = 2k CONDITIONS CINT = C1 + C2 + C3 VO = ±10V IIN = 0, CIN = 50pF VS = +4.75/10 to +18/18V MIN TYP MAX UNITS % ppm/ °C % µA mV µV/ °C µV/V nV/µ s fA mV µV/ °C µV/V nV/ Hz pF ppm/ °C pF pF pF V V mA pF
VO = (IIN )(TINT)/CINT ±5 +25/17 ± 25 ±0.005 ±100 5 ±20 ± 30 150 750 1 100 See Typical Curve ± 0.5 ±5 10 10 80 100 ± 25 10 30 60 (V+)1.3 (V)+2.6 ± 20 500 See Typical Curve 2 3 3 6 2 0.5 2 0 100 +4.75 10 +15 15 4.1 1.6 0.2 2.3 +18 18 5.5 2.2 5.5 0.8 ±750 ±5 100
S1, S2 Open
VS = +4.75/10 to +18/18V f = 1kHz
120
(V+)3 (V)+3
MHz V/µs V/µs µs V V µA µA ns V V mA mA mA mA °C °C °C/W °C/W
10V Step (TTL/CMOS Compatible) (Logic High) (Logic Low) VIH = 5V VIL = 0V
40 55 100 150
85 125
NOTES: (1) Standard test timing: 1ms integration, 200µs hold, 100µs reset. (2) Hold mode output voltage after 1ms integration of zero input current. Includes op amp offset voltage, integration of input error current and switch charge injection effects.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
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IVC102
2
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V+ to V ........... 36V Logic Input Voltage .... V to V+ Output Short Circuit to Ground ..... Continuous Operating Temperature ....... 40°C to +125°C Storage Temperature ..... 55°C to +125°C Lead Temperature (soldering, 10s) ....... 300° C
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PIN CONNECTIONS
Top View 14-Pin DIP/ SO-14 Surface Mount
Analog Ground IIN Cn I C1 C2
N3
2 1 3 4 5 6 7
14 V+ D 13 igital Ground
12 S2 11 V1 9 0 8
VO N
C
C
NC = No Internal Connection Connect to Analog Ground for Lowest Noise
PACKAGE INFORMATION
PRODUCT IVC102P IVC102U PACKAGE 14-Pin DIP SO-14 Surface Mount PACKAGE DRAWING NUMBER(1) 010 235
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book.
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3
IVC102
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IV-1
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