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Details, datasheet, quote on part number:JM38510/65601BRA
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Datasheet text preview:
SCLS136D - DECEMBER 1982 - REVISED AUGUST 2003
SN54HC273, SN74HC273 OCTAL D TYPE FLIP FLOPS WITH CLEAR
D D D D D D D
Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 12 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max Contain Eight Flip-Flops With Single-Rail Outputs
D Direct Clear Input D Individual Data Input to Each Flip-Flop D Applications Include:
- Buffer/Storage Registers - Shift Registers - Pattern Generators
description
SN54HC273 . . . J OR W PACKAGE SN74HC273 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) SN54HC273 . . . FK PACKAGE (TOP VIEW)
1D 1Q CLR VCC
CLR 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK
2D 2Q 3Q 3D 4D
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
8Q 8D 7D 7Q 6Q 6D
description/ordering information
These circuits are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input. ORDERING INFORMATION
TA PDIP - N SOIC - DW -40°C to 85°C SOP - NS SSOP - DB PACKAGE Tube of 20 Tube of 25 Reel of 2000 Reel of 2000 Reel of 2000 Tube of 70 TSSOP - PW CDIP - J -55°C to 125°C 125 C CFP - W LCCC - FK Reel of 2000 Reel of 250 Tube of 20 Tube of 85 Tube of 55 ORDERABLE PART NUMBER SN74HC273N SN74HC273DW SN74HC273DWR SN74HC273NSR SN74HC273DBR SN74HC273PW SN74HC273PWR SN74HC273PWT SNJ54HC273J SNJ54HC273W SNJ54HC273FK SNJ54HC273J SNJ54HC273W HC273 HC273 HC273 HC273 TOP-SIDE MARKING SN74HC273N
SNJ54HC273FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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4Q GND CLK 5Q 5D
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
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SCLS136D - DECEMBER 1982 - REVISED AUGUST 2003
SN54HC273, SN74HC273 OCTAL D TYPE FLIP FLOPS WITH CLEAR
description/ordering information (continued)
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
FUNCTION TABLE (each flip-flop) INPUTS CLR L H H H CLK X L D X H L X OUTPUT Q L H L Q0
logic diagram (positive logic)
1D CLK 11 3 2D 4 3D 7 4D 8 5D 13 6D 14 7D 17 8D 18
1D C1 R CLR 1 2 1Q
1D C1 R
1D C1 R
1D C1 R
1D C1 R
1D C1 R
1D C1 R
1D C1 R
5 2Q
6 3Q
9 4Q
12 5Q
15 6Q
16 7Q
19 8Q
logic diagram, each flip-flop (positive logic)
C C
D
TG C C TG
TG Q C C
CLK(I)
C C C
TG
C R
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SCLS136D - DECEMBER 1982 - REVISED AUGUST 2003
SN54HC273, SN74HC273 OCTAL D TYPE FLIP FLOPS WITH CLEAR
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC273 MIN VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO t/v Low-level input voltage Input voltage Output voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 4.5 V VCC = 6 V 0 0 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 0 0 NOM 5 MAX 6 SN74HC273 MIN 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 ns V V V V NOM 5 MAX 6 UNIT V
High-level input voltage
Input transition rise/fall time
TA Operating free-air temperature -55 125 -40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SCLS136D - DECEMBER 1982 - REVISED AUGUST 2003
SN54HC273, SN74HC273 OCTAL D TYPE FLIP FLOPS WITH CLEAR
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 2V IOH = -20 µA VOH VI = VIH or VIL IOH = -4 mA IOH = -5.2 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC Ci VI = VCC or 0 VI = VCC or 0, IO = 0 4.5 V 6V 4.5 V 6V 2V 4.5 V 6V 4.5 V 6V 6V 6V 2 V to 6 V 3 MIN 1.9 4.4 5.9 3.98 5.48 TA = 25°C TYP MAX 1.998 4.499 5.999 4.3 5.8 0.002 0.001 0.001 0.17 0.15 ±0.1 0.1 0.1 0.1 0.26 0.26 ±100 8 10 SN54HC273 MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1000 160 10 MAX SN74HC273 MIN 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1000 80 10 nA µA pF V V MAX UNIT
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC 2V fclock Clock frequency 4.5 V 6V 2V CLR low tw Pulse duration CLK high or low 4.5 V 6V 2V 4.5 V 6V 2V Data tsu Setup time before CLK CLR inactive 4.5 V 6V 2V 4.5 V 6V 2V th Hold time, data after CLK CLK 4.5 V 6V 80 16 14 80 16 14 100 20 17 100 20 17 0 0 0 TA = 25°C MIN MAX 5 27 32 120 24 20 120 24 20 150 30 25 150 30 25 0 0 0 SN54HC273 MIN MAX 4 18 21 100 20 17 100 20 17 125 25 21 125 25 21 0 0 0 ns ns ns SN74HC273 MIN MAX 4 21 25 MHz UNIT
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SCLS136D - DECEMBER 1982 - REVISED AUGUST 2003
SN54HC273, SN74HC273 OCTAL D TYPE FLIP FLOPS WITH CLEAR
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V fmax 4.5 V 6V 2V tPHL CLR Any 4.5 V 6V 2V tpd CLK Any 4.5 V 6V 2V tt Any 4.5 V 6V MIN 5 27 32 TA = 25°C TYP MAX 11 50 60 55 15 12 56 15 13 38 8 6 160 32 27 160 32 27 75 15 13 SN54HC273 MIN 4 18 21 240 48 41 240 48 41 110 22 19 MAX SN74HC273 MIN 4 21 25 200 40 34 200 40 34 95 19 16 ns ns ns MHz MAX UNIT
operating characteristics, TA = 25°C
PARAMETER Cpd Power dissipation capacitance per flip-flop TEST CONDITIONS No load TYP 35 UNIT pF
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