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Details, datasheet, quote on part number:JM38510/65602BRA
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Datasheet text preview:
SN54HC374, SN74HC374 OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS
SCLS141E - DECEMBER 1982 - REVISED AUGUST 2003
D Wide Operating Voltage Range of 2 V to 6 V D High-Current 3-State True Outputs Can
Drive Up To 15 LSTTL Loads
D Eight D-Type Flip-Flops in a Single Package D Full Parallel Access for Loading
SN54HC374 . . . J OR W PACKAGE SN74HC374 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW)
D D D D
Low Power Consumption, 80-µA Max ICC Typical tpd = 14 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max
SN54HC374 . . . FK PACKAGE (TOP VIEW)
OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK
1D 1Q OE VCC 8Q 2D 2Q 3Q 3D 4D
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
8D 7D 7Q 6Q 6D
description/ordering information
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the 'HC374 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs. An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. ORDERING INFORMATION
TA PDIP - N SOIC - DW -40°C to 85 C 85°C SOP - NS SSOP - DB TSSOP - PW CDIP - J -55°C to 125 C 125°C CFP - W LCCC - FK PACKAGE Tube of 20 Tube of 25 Reel of 2000 Reel of 2000 Reel of 2000 Tube of 2000 Reel of 250 Tube of 20 Tube of 85 Tube of 55 ORDERABLE PART NUMBER SN74HC374N SN74HC374DW SN74HC374DWR SN74HC374NSR SN74HC374DBR SN74HC374PWR SN74HC374PWT SNJ54HC374J SNJ54HC374W SNJ54HC374FK HC374 SNJ54HC374J SNJ54HC374W HC374 HC374 HC374 TOP-SIDE MARKING SN74HC374N
SNJ54HC374FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
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4Q GND CLK 5Q 5D
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SCLS141E - DECEMBER 1982 - REVISED AUGUST 2003
SN54HC374, SN74HC374 OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS
description/ordering information (continued)
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE (each flip-flop) INPUTS OE L L L H CLK H or L X D H L X X OUTPUT Q H L Q0 Z
logic diagram (positive logic)
OE 1
CLK
11 C1 2
1D
3
1D
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC374, SN74HC374 OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS
SCLS141E - DECEMBER 1982 - REVISED AUGUST 2003
recommended operating conditions (see Note 3)
SN54HC374 MIN VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO t/v Low-level input voltage Input voltage Output voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 4.5 V VCC = 6 V 0 0 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 0 0 NOM 5 MAX 6 SN74HC374 MIN 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 ns V V V V NOM 5 MAX 6 UNIT V
High-level input voltage
Input transition rise/fall time
TA Operating free-air temperature -55 125 -40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 2V IOH = -20 µA VOH VI = VIH or VIL IOH = -6 mA IOH = -7.8 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 6 mA IOL = 7.8 mA II IOZ ICC Ci VI = VCC or 0 VO = VCC or 0 VI = VCC or 0, IO = 0 4.5 V 6V 4.5 V 6V 2V 4.5 V 6V 4.5 V 6V 6V 6V 6V 2 V to 6 V 3 TA = 25°C MIN TYP MAX 1.9 4.4 5.9 3.98 5.48 1.998 4.499 5.999 4.3 5.8 0.002 0.001 0.001 0.17 0.15 ±0.1 ±0.01 0.1 0.1 0.1 0.26 0.26 ±100 ±0.5 8 10 SN54HC374 MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1000 ±10 160 10 MAX SN74HC374 MIN 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1000 ±5 80 10 nA µA µA pF V V MAX UNIT
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SCLS141E - DECEMBER 1982 - REVISED AUGUST 2003
SN54HC374, SN74HC374 OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC 2V fclock Clock frequency 4.5 V 6V 2V tw Pulse duration, CLK high or low 4.5 V 6V 2V tsu Setup time, data before CLK 4.5 V 6V 2V th Hold time, data after CLK CLK 4.5 V 6V 80 16 14 100 20 17 10 5 5 TA = 25°C MIN MAX 6 30 35 120 24 20 150 30 25 13 5 5 SN54HC374 MIN MAX 4 20 24 100 20 17 125 25 21 12 5 5 ns ns ns SN74HC374 MIN MAX 5 24 28 MHz UNIT
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V fmax 4.5 V 6V 2V tpd CLK Any Q 4.5 V 6V 2V ten OE Any Q 4.5 V 6V 2V tdis OE Any Q 4.5 V 6V 2V tt Any Q 4.5 V 6V TA = 25°C MIN TYP MAX 6 30 35 12 60 70 63 17 15 60 16 14 36 17 16 28 8 6 180 36 31 150 30 26 150 30 26 60 12 10 SN54HC374 MIN 4 20 24 270 54 46 225 45 38 225 45 38 90 18 15 MAX SN74HC374 MIN 5 24 28 225 45 38 190 38 32 190 38 32 75 15 13 ns ns ns ns MHz MAX UNIT
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC374, SN74HC374 OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS
SCLS141E - DECEMBER 1982 - REVISED AUGUST 2003
switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V fmax 4.5 V 6V 2V tpd CLK Any Q 4.5 V 6V 2V ten OE Any Q 4.5 V 6V 2V tt Any Q 4.5 V 6V MIN 6 30 35 TA = 25°C TYP MAX 12 60 70 80 22 19 70 25 22 45 17 13 230 46 39 200 40 34 210 42 36 345 69 58 300 60 51 315 63 53 SN54HC374 MIN MAX SN74HC374 MIN 5 24 28 290 58 49 250 50 43 265 53 45 ns ns ns MHz MAX UNIT
operating characteristics, TA = 25°C
PARAMETER Cpd Power dissipation capacitance per flip-flop TEST CONDITIONS No load TYP 100 UNIT pF
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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