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Details, datasheet, quote on part number:JM38510/65802BFA
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Datasheet text preview:
SN54HC138, SN74HC138 3 LINE TO 8 LINE DECODERS/DEMULTIPLEXERS
SCLS107E - DECEMBER 1982 - REVISED SEPTEMBER 2003
D Targeted Specifically for High-Speed D D D D D D D
Memory Decoders and Data-Transmission Systems Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 15 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception
SN54HC138 . . . J OR W PACKAGE SN74HC138 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW)
A B C G2A G2B G1 Y7 GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6
description/ordering information
The 'HC138 devices are designed to be used in high-performance memory-decoding or datarouting applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
SN54HC138 . . . FK PACKAGE (TOP VIEW)
B A NC VCC Y0 C G2A NC G2B G1
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
Y1 Y2 NC Y3 Y4
NC - No internal connection
ORDERING INFORMATION
TA PDIP - N PACKAGE Tube of 25 Tube of 40 SOIC - D -40°C to 85 C 85°C SOP - NS SSOP - DB Reel of 2500 Reel of 250 Reel of 2000 Reel of 2000 Tube of 90 TSSOP - PW CDIP - J -55°C to 125 C 125°C CFP - W LCCC - FK Reel of 2000 Reel of 250 Tube of 25 Tube of 150 Tube of 55 ORDERABLE PART NUMBER SN74HC138N SN74HC138D SN74HC138DR SN74HC138DT SN74HC138NSR SN74HC138DBR SN74HC138PW SN74HC138PWR SN74HC138PWT SNJ54HC138J SNJ54HC138W SNJ54HC138FK SNJ54HC138J SNJ54HC138W HC138 HC138 HC138 HC138 TOP-SIDE MARKING SN74HC138N
SNJ54HC138FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
Y7 GND NC Y6 Y5
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SN54HC138, SN74HC138 3 LINE TO 8 LINE DECODERS/DEMULTIPLEXERS
SCLS107E - DECEMBER 1982 - REVISED SEPTEMBER 2003
description/ordering information (continued)
The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
FUNCTION TABLE INPUTS ENABLE G1 X X L H H H H H H H H G2A H X X L L L L L L L L G2B X H X L L L L L L L L C X X X L L L L H H H H SELECT B X X X L L H H L L H H A X X X L H L H L H L H Y0 H H H L H H H H H H H Y1 H H H H L H H H H H H Y2 H H H H H L H H H H H OUTPUTS Y3 H H H H H H L H H H H Y4 H H H H H H H L H H H Y5 H H H H H H H H L H H Y6 H H H H H H H H H L H Y7 H H H H H H H H H H L
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC138, SN74HC138 3 LINE TO 8 LINE DECODERS/DEMULTIPLEXERS
SCLS107E - DECEMBER 1982 - REVISED SEPTEMBER 2003
logic diagram (positive logic)
15 1 14 Y1
Y0
A
B
2 13 Y2
C
3
12
Y3
11
Y4
10 G1 6 9
Y5
Y6 G2A 4 7 Y7
G2B
5
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
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3
SN54HC138, SN74HC138 3 LINE TO 8 LINE DECODERS/DEMULTIPLEXERS
SCLS107E - DECEMBER 1982 - REVISED SEPTEMBER 2003
recommended operating conditions (see Note 3)
SN54HC138 MIN VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO t/v Low-level input voltage Input voltage Output voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 4.5 V VCC = 6 V 0 0 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 0 0 NOM 5 MAX 6 SN74HC138 MIN 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 ns V V V V NOM 5 MAX 6 UNIT V
High-level input voltage
Input transition rise/fall time
TA Operating free-air temperature -55 125 -40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 2V IOH = -20 µA VOH VI = VIH or VIL IOH = -4 mA IOH = -5.2 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC Ci VI = VCC or 0 VI = VCC or 0, IO = 0 4.5 V 6V 4.5 V 6V 2V 4.5 V 6V 4.5 V 6V 6V 6V 2 V to 6 V 3 TA = 25°C MIN TYP MAX 1.9 4.4 5.9 3.98 5.48 1.998 4.499 5.999 4.3 5.8 0.002 0.001 0.001 0.17 0.15 ±0.1 0.1 0.1 0.1 0.26 0.26 ±100 8 10 SN54HC138 MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1000 160 10 MAX SN74HC138 MIN 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1000 80 10 nA µA pF V V MAX UNIT
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC138, SN74HC138 3 LINE TO 8 LINE DECODERS/DEMULTIPLEXERS
SCLS107E - DECEMBER 1982 - REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V A, B, or C tpd Enable Any Y Any Y 4.5 V 6V 2V 4.5 V 6V 2V tt Any 4.5 V 6V MIN TA = 25°C TYP MAX 67 18 15 66 18 15 38 8 6 180 36 31 155 31 26 75 15 13 SN54HC138 MIN MAX 270 54 46 235 47 40 110 22 19 SN74HC138 MIN MAX 225 45 38 195 39 33 95 19 16 ns ns UNIT
operating characteristics, TA = 25°C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load TYP 85 UNIT pF
PARAMETER MEASUREMENT INFORMATION
From Output Under Test Test Point CL = 50 pF (see Note A) In-Phase Output Input VCC 50% tPLH 50% 10% tPHL Out-of-Phase Output 90% 50% 10% tf 90% tr Input 50% 10% 90% 90% VCC 50% 10% 0 V tf tPLH 50% 10% 90% tr 50% 0V tPHL 90% VOH 50% 10% VOL tf VOH VOL
LOAD CIRCUIT
tr VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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· DALLAS, TEXAS 75265
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