|
Details, datasheet, quote on part number:JM38510/65852BEA
| |
Datasheet text preview:
SN54HCT138, SN74HCT138 3 LINE TO 8 LINE DECODERS/DEMULTIPLEXERS
SCLS171E - MARCH 1984 - REVISED SEPTEMBER 2003
D D D D D
Operating Voltage Range of 4.5 V to 5.5 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 17 ns ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max D Inputs Are TTL-Voltage Compatible D Designed Specifically for High-Speed D
Memory Decoders and Data Transmission Systems Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception
SN54HCT138 . . . FK PACKAGE (TOP VIEW)
NC - No internal connection
description/ordering information
The 'HCT138 devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. ORDERING INFORMATION
TA PDIP - N PACKAGE Tube of 25 Tube of 40 SOIC - D -40°C to 85°C SOP - NS Reel of 2500 Reel of 250 Reel of 2000 Tube of 90 TSSOP - PW CDIP - J -55°C to 125 C 125°C CFP - W Reel of 2000 Reel of 250 Tube of 25 Tube of 150 ORDERABLE PART NUMBER SN74HCT138N SN74HCT138D SN74HCT138DR SN74HCT138DT SN74HCT138NSR SN74HCT138PW SN74HCT138PWR SN74HCT138PWT SNJ54HCT138J SNJ54HCT138W SNJ54HCT138J SNJ54HCT138W HT138 HCT138 HCT138 TOP-SIDE MARKING SN74HCT138N
LCCC - FK Tube of 55 SNJ54HCT138FK SNJ54HCT138FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
Y7 GND NC Y6 Y5
A B C G2A G2B G1 Y7 GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6
B A NC VCC Y0 C G2A NC G2B G1
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
SN54HCT138 . . . J OR W PACKAGE SN74HCT138 . . . D, N, NS, OR PW PACKAGE (TOP VIEW)
Y1 Y2 NC Y3 Y4
1
SN54HCT138, SN74HCT138 3 LINE TO 8 LINE DECODERS/DEMULTIPLEXERS
SCLS171E - MARCH 1984 - REVISED SEPTEMBER 2003
description/ordering information (continued)
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low (G) and one active-high (G) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
FUNCTION TABLE INPUTS ENABLE G1 X X L H H H H H H H H G2A H X X L L L L L L L L G2B X H X L L L L L L L L C X X X L L L L H H H H SELECT B X X X L L H H L L H H A X X X L H L H L H L H Y0 H H H L H H H H H H H Y1 H H H H L H H H H H H Y2 H H H H H L H H H H H OUTPUTS Y3 H H H H H H L H H H H Y4 H H H H H H H L H H H Y5 H H H H H H H H L H H Y6 H H H H H H H H H L H Y7 H H H H H H H H H H L
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HCT138, SN74HCT138 3 LINE TO 8 LINE DECODERS/DEMULTIPLEXERS
SCLS171E - MARCH 1984 - REVISED SEPTEMBER 2003
logic diagram (positive logic)
15 1 14 Y1
Y0
A
B
2 13 Y2
C
3
12
Y3
11
Y4
10 G1 6 9
Y5
Y6 G2A 4 7 Y7
G2B
5
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SN54HCT138, SN74HCT138 3 LINE TO 8 LINE DECODERS/DEMULTIPLEXERS
SCLS171E - MARCH 1984 - REVISED SEPTEMBER 2003
recommended operating conditions (see Note 3)
SN54HCT138 MIN VCC VIH VIL VI VO t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Input transition rise/fall time VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 4.5 2 0.8 0 0 VCC VCC 500 0 0 NOM 5 MAX 5.5 SN74HCT138 MIN 4.5 2 0.8 VCC VCC 500 NOM 5 MAX 5.5 UNIT V V V V V ns
TA Operating free-air temperature -55 125 -40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VOH VOL II ICC ICC Ci TEST CONDITIONS VI = VIH or VIL VI = VIH or VIL VI = VCC or 0 VI = VCC or 0, IOH = -20 µA IOH = -4 mA IOL = 20 µA IOL = 4 mA VCC 4.5 V 4.5 V 5.5 V 5.5 V 5.5 V 4.5 V to 5.5 V 1.4 3 MIN 4.4 3.98 TA = 25°C TYP MAX 4.499 4.3 0.001 0.17 ±0.1 0.1 0.26 ±100 8 2.4 10 SN54HCT138 MIN 4.4 3.7 0.1 0.4 ±1000 160 3 10 MAX SN74HCT138 MIN 4.4 3.84 0.1 0.33 ±1000 80 2.9 10 V nA µA mA pF V MAX UNIT
IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) A, B, or C tpd Enable tt Any Y Y TO (OUTPUT) Any Y VCC 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V MIN TA = 25°C TYP MAX 23 17 22 18 12 11 36 32 33 30 15 14 SN54HCT138 MIN MAX 54 49 50 45 22 20 SN74HCT138 MIN MAX 45 34 42 38 19 17 ns ns UNIT
operating characteristics, TA = 25°C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load TYP 85 UNIT pF
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HCT138, SN74HCT138 3 LINE TO 8 LINE DECODERS/DEMULTIPLEXERS
SCLS171E - MARCH 1984 - REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
From Output Under Test Test Point CL = 50 pF (see Note A) In-Phase Output 3V Input 1.3 V tPLH 1.3 V 10% tPHL Out-of-Phase Output 90% 1.3 V 10% tf 90% tr Input 1.3 V 0.3 V 2.7 V 2.7 V 3V 1.3 V 0.3 V 0 V tf tPLH 1.3 V 10% 90% tr VOH VOL 1.3 V 0V tPHL 90% VOH 1.3 V 10% V OL tf
LOAD CIRCUIT
tr VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
|
|
