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Part: MSP-EVK430B330
Category:
Microcontrollers
-> Ultra-Low Power Microcontrollers
Description: ti MSP430P337, 16-Bit Ultra-low-power Microcontroller, 32kB Otp, 1KB RAM, Usart, HW Multiplier, 120 Segment LCD
Company: Texas Instruments, Inc.
Datasheet: Download MSP-EVK430B330 datasheet File size : 684 kB
Request For quote: Find where to buy MSP-EVK430B330
Datasheet text preview:
MSP430x33x MIXED SIGNAL MICROCONTROLLERS
SLAS163 FEBRUARY 1998
D D D D D D D D D D D D D D D
VCC1 CIN TP0.0 TP0.1 TP0.2 TP0.3 TP0.4 TP0.5 P0.0 P0.1/RXD P0.2/TXD P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 VSS2 VCC2 NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
VSS1 Xin Xout/TCLK XBUF RST/NMI TCK T MS TDI/VPP TDO/TDI R33 R23 R13 R03 S29/O29/CMPI S28/O28 S27/O27 S26/O26 S25/O25 S24/O24 S23/O23
D D
Low Supply Voltage Range 2.5 V 5.5 V Low Operation Current, 400 mA at 1 MHz, 3V Ultra-Low Power Consumption (Standby Mode Down to 0.1 µA) Five Power-Saving Modes Wake Up from Standby Mode in 6 µS 16-Bit RISC Architecture, 300 ns Instruction Cycle Time Single Common 32 kHz Crystal, Internal System Clock up to 3.8 MHz Integrated LCD Driver for up to 120 Segments Integrated Hardware Multiplier Performs Signed, Unsigned, and MAC Operations for Operands Up to 16 X 16 Bits Serial Communication Interface (USART), Select Asynchronous UART or Synchronous SPI by Software Slope A/D Converter Using External Components 16-Bit Timer With Five Capture/Compare Registers Programmable Code Protection by Security Fuse Family Members Include: MSP430C336 24 KB ROM, 1 KB RAM MSP430C337 32 KB ROM, 1 KB RAM MSP430P337 32 KB OTP, 1 KB RAM EPROM Version Available for Prototyping: PMS430E337 Serial On-Board Programming Available in 100 Pin Quad Flat-Pack (QFP) Package, 100 Pin Ceramic Quad Flat-Pack (CFP) package (EPROM Version)
PJM or HFD PACKAGE (TOP VIEW)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC S22/O22 S21/O21 S20/O20 S19/O19 S18/O18 S17/O17 S16/O16 S15/O15 S14/O14 S13/O13 S12/O12 S11/O11 S10/O10 S9/O9 S8/O8 S7/07 S6/O6 S5/O5 S4/O4 S3/O3 S2/O2 S1 S0 COM0 COM1 COM2 COM3 VSS3 P4.7/URXD
NC No internal connection
description
The Texas Instruments MSP430 series is a ultra low-power microcontroller family consisting of several devices which features different sets of modules targeted to various applications. The controller is designed to be battery operated for an extended application lifetime. With the 16-bit RISC architecture, 16 integrated registers on the CPU, and the constant generator, the MSP430 achieves maximum code efficiency. The digital-controlled oscillator, together with the frequency lock loop (FLL), provides a fast wake up from a low-power mode to an active mode in less than 6 ms. The MSP430x33x series micro-controllers have built in hardware multiplication and communication capability using asynchronous (UART) and synchronous protocols. Typical applications of the MSP430 family include electronic gas, water, and electric meters and other sensor systems that capture analog signals, converts them to digital values, processes, displays, or transmits them to a host system.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2/TACLK P3.3/TA0 P3.4/TA1 P3.5/TA2 P3.6/TA3 P3.7/TA4 P4.0 P4.1 P4.2/STE P4.3/SIMO P4.4/SOMI P4.5/UCLK P4.6/UTXD Copyright © 1998, Texas Instruments Incorporated
1
MSP430x33x MIXED SIGNAL MICROCONTROLLER
SLAS163 FEBRUARY 1998
AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC QFP (PJM) MSP430C336IPJM MSP430C337IPJM MSP430P337IPJM -- CERAMIC QFP (HFD) -- PMS430E337HFD
2 40°C to 85°C to 85°C 25°C
Template Release Date: 71194
functional block diagram
XIN XOut XBUF VCC1 VCC2 VSS1 VSS2 RST/NMI P4.0 P4.7 P2.x P1.x P3.0 P3.7 P0.0 P0.7
8 Oscillator FLL System Clock TDI TDO MAB, 16 Bit ACLK MCLK 24/32 kB ROM 32 kB OPT or EPROM C: ROM P: OTP E: EPROM 1024B RAM SRAM Power-onReset I/O Port 1x8 Digital I/O's
8 I/O Port I/O Port 1x8 Digital I/O's I/O Port 8 I/O's, All With Interr. Cap. 3 Int. Vectors RXD, TXD
POST OFFICE BOX 655303 · DALLAS, TEXAS 75265
2x8 I/O's All Interr. Cap. 2 Int. Vectors
USART
TimerA
MAB, 4 Bit
CPU Incl. 16 Reg.
Test JTAG MDB, 16 Bit Bus Conv
MCB MDB, 8 Bit
TMS TCK Multiplier MPY MPYS MAC 16x16 Bit 8x8 Bit Watchdog timer 15/16 Bit TimerA 16 Bit PWM TACLK TA04 UTXD URXD UCLK USART UART or SPI Function 8 Bit Timer/Counter Timer/Port Applications A/D Conv. Timer, O/P TXD RXD 6 Basic Timer1 f LCD CMPI LCD 120 Segments 1, 2, 3, 4 MUX Com03 S028/O228 S29/O29/CMPI
STE SIMO SOMI
TP0.00.5 CIN
R03 R23 R13 R33
MSP430x33x MIXED SIGNAL MICROCONTROLLERS
SLAS163 FEBRUARY 1998
Terminal Functions
TERMINAL NAME CIN COM03 P0.0 P0.1/RXD P0.2/TXD P0.3P0.7 P1.0P1.7 P2.0P2.7 P3.0, P3.1 P3.2/TACLK P3.3/TA0 P3.4/TA1 P3.5/TA2 P3.6/TA3 P3.7/TA4 P4.0 P4.1 P4.2/STE P4.3/SIMO P4.4/SOMI P4.5/UCLK P4.6/UTXD P4.7/URXD R03 R13 R23 R33 RST/NMI S0 S1 S2/O2S5/O5 S6/O6S9/O9 S10/O10S13/O13 S14/O14S17/O17 S18/O18S21/O21 S22/O22S25/O25 S26/O26S29/O29/CMPI TCK TDI/VPP NO. 2 5653 9 10 11 1216 1724 2527, 3135 36,37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 88 89 90 91 96 57 58 5962 6366 6770 7174 7578 79, 8183 8487 95 93 I/O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I O I O O O O O O O O O I I DESCRIPTION Input port. CIN is used as an enable for counter TPCNT1 timer/port Common outputs. COMM0-3 are used for LCD backplanes LCD General purpose digital I/O General purpose digital I/O, receive digital Input port 8-bit timer/counter General purpose digital I/O, transmit data output port 8-bit timer/counter Five general purpose digital I/Os, bit 3-7 Eight general purpose digital I/Os, bit 0-7 Eight general purpose digital I/Os, bit 0-7 Two general purpose digital I/Os, bit 0 and bit 1 General purpose digital I/O, clock input timer A General purpose digital I/O, capture I/O, or PWM output port Timer_A CCR0 General purpose digital I/O, capture I/O, or PWM output port Timer_A CCR1 General purpose digital I/O, capture I/O, or PWM output port Timer_A CCR2 General purpose digital I/O, capture I/O, or PWM output port Timer_A CCR3 General purpose digital I/O, capture I/O, or PWM output port Timer_A CCR4 General purpose digital I/O, bit 0 General purpose digital I/O, bit 1 General purpose digital I/O, slave transmit enable USART/SPI mode General purpose digital I/O, slave in/master out USART/SPI mode General purpose digital I/O, master in/slave out USART/SPI mode General purpose digital I/O, external clock input USART General purpose digital I/O, transmit data out USART/UART mode General purpose digital I/O, receive data in USART/UART mode Input port of fourth positive (lowest) analog LCD level (V5) LCD Input port of third most positive analog LCD level (V3 of V4) LCD Input port of second most positive analog LCD level (V2) LCD Output of most positive analog LCD level (V1) LCD Reset input or non-maskable interrupt input port Segment line S0 LCD Segment line S1 LCD Segment lines S2 to S5 or digital output ports, O2-O5, group 1 LCD Segment lines S6 to S9 or digital output ports O6-O9, group 2 LCD Segment lines S10 to S13 or digital output ports O10-O13, group 3 LCD Segment lines S14 to S17 or digital output ports O14-O17, group 4 LCD Segment lines S18 to S21 or digital output ports O18-O21, group 5 LCD Segment line S22 to S25 or digital output ports O22-O25, group 6 LCD Segment line S26 to S29 or digital output ports O26-O29, group 7 LCD. Segment line S29 can be used as comparator input port CMPI timer/port Test clock. TCK is the clock input port for device programming and test Test data input. TDI/VPP is used as a data input port or input for programming voltage
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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