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Details, datasheet, quote on part number:OPA683
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OPA683
OPA 683
OPA 683
SBOS221B NOVEMBER 2001 -- REVISED JUNE 2002
Very Low-Power, Current Feedback OPERATIONAL AMPLIFIER With Disable
FEATURES
q q q q q q q q q REDUCED BANDWIDTH CHANGE VERSUS GAIN 150MHz BANDWIDTH G = +2 > 90MHz BANDWIDTH TO GAIN > +10 LOW DISTORTION: < 69dBc at 5MHz HIGH OUTPUT CURRENT: 110mA SINGLE +5V TO +12V SUPPLY OPERATION DUAL ±2.5V TO ±6V SUPPLY OPERATION LOW SUPPLY CURRENT: 0.94mA LOW SHUTDOWN CURRENT: 100µA
APPLICATIONS
q q q q q q q LOW POWER BROADCAST VIDEO DRIVERS EQUALIZING FILTERS SAW FILTER HIGH GAIN POST AMPLIFIERS SHORT LOOP ADSL CO DRIVERS MULTICHANNEL SUMMING AMPLIFIERS PROFESSIONAL CAMERAS ADC INPUT DRIVERS
DESCRIPTION
The OPA683 provides a new level of performance in very lowpower, wideband, current feedback amplifiers. This CFBplus amplifier is among the first to use an internally closed-loop input buffer stage that enhances performance significantly over earlier lowpower CFB amplifiers. While retaining the benefits of very low power operation, this new architecture provides many of the advantages of a more ideal CFB amplifier. The closed-loop input stage buffer gives a very low and linearized impedance path at the inverting input to sense the feedback error current. This improved inverting input impedance gives exceptional bandwidth retention to much higher gains and improved harmonic distortion over earlier solutions limited by inverting input linearity. Beyond simple high gain applications, the OPA683 CFBplus amplifier can allow the gain setting element to be set with considerable freedom from amplifier bandwidth interaction. This allows frequency response peaking elements to be added, multiple input inverting summing circuits to
have greater bandwidth, and low-power line drivers to meet the demanding requirements of studio cameras and broadcast video. The output capability for the OPA683 also sets a new mark in performance for very low-power current feedback amplifiers. Delivering a full ±4Vp-p swing on ±5V supplies, the OPA683 also has the output current to support this swing into a 100 load. This minimal output headroom requirement is complemented by a similar 1.2V input stage headroom giving exceptional capability for single +5V operation. The OPA683's low 0.94mA supply current is precisely trimmed at 25°C. This trim, along with low shift over temperature and supply voltage, gives a very robust design over a wide range of operating conditions. System power may be further reduced by using the optional disable control pin. Leaving this disable pin open, or holding it HIGH, gives normal operation. If pulled LOW, the OPA683 supply current drops to less than 100µA while the I/O pins go to a high impedance state.
V+
OPA683 BANDWIDTH vs GAIN 9 6
+
G=2 G=5
VO
Normalized Gain (dB)
3 0 3 6 9 12 15 18 21 1 RF = 1.2k G = 10 G = 20 G = 50 G = 100 10 Frequency (MHz)
V IERR RF
Z(S) IERR
RG
100
200
Low-Power
Patent Pending
Amplifier
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2001, Texas Instruments Incorporated
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ABSOLUTE MAXIMUM RATINGS(1)
Power Supply ....... ±6.5VDC Internal Power Dissipation ......... See Thermal Information Differential Input Voltage ......... ±1.2V Input Voltage Range .......... ±VS Storage Temperature Range: ID, IDBV ....... 40°C to +125°C Lead Temperature (soldering, 10s) .... +300°C Junction Temperature (TJ ) .. +175°C NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
OPA683 RELATED PRODUCTS
SINGLES OPA684 OPA691 OPA685 DUALS OPA2683 OPA2691 -- TRIPLES OPA3684 OPA3691 -- QUADS OPA4684 -- -- FEATURES Low-Power CFBplus High Slew Rate CFB > 500MHz CFB
PACKAGE /ORDERING INFORMATION
PRODUCT OPA683 PACKAGE-LEAD SO-8 PACKAGE DESIGNATOR(1) D SPECIFIED TEMPERATURE RANGE 40°C to +85°C PACKAGE MARKING OPA683D ORDERING NUMBER OPA683ID OPA683IDR OPA683IDBVT OPA683IDBVR TRANSPORT MEDIA, QUANTITY Rails,100 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 3000
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OPA683
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SOT23-6
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DBV
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40°C to +85°C
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A83
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NOTES: (1) For the most current specifications, and package information, refer to our web site at www.ti.com.
PIN CONFIGURATION
Top View SO-8 Top View SOT23-6
Output
1
6
+VS
VS
NC Inverting Input Noninverting Input VS 1 2 3 4 8 7 6 5 DIS
2
5
DIS
Noninverting Input
+VS Output NC
3
4
Inverting Input
6
5
4
NC = No Connection
A83
1 2 3 Pin Orientation/Package Marking
2
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OPA683
SBOS221B
ELECTRICAL CHARACTERISTICS: VS = ±5V
RF = 1.2k, RL = 1k, and G = +2, (see Figure 1 for AC performance only), unless otherwise noted. OPA683ID, IDBV TYP +25°C 200 150 121 94 72 37 1.8 63 540 400 4.6 7.8 63 65 67 74 4.4 5.1 11.6 0.06 0.03 700 ±1.5 ±2.0 ±3.0 +25°C(1) MIN/MAX OVER TEMPERATURE 0°C to 70°C(2) 40°C to +85°C(2) MIN/ TEST MAX LEVEL(3) typ min typ typ typ min max typ mi n mi n typ typ max max max max max max max typ typ min max max max max max max min min typ typ min min min typ typ typ typ typ typ typ typ min max max typ max max min typ typ typ typ C B C B C B B C B B C C B B B B B B B C C A A B A B A B A A C C A A A C C C C C C C C A A A C A A A A C C C
PARAMETER AC PERFORMANCE (See Figure 1) Small-Signal Bandwidth (VO = 0.5Vp-p)
CONDITIONS G = +1, RF = 1.2k G = +2, RF = 1.2k G = +5, RF = 1.2k G = +10, RF = 1.2k G = +20, RF = 1.2k G = +2, VO = 0.5Vp-p, RF = 1.2k RF = 1.2k, VO = 0.5Vp-p G = +2, VO = 4Vp-p G = 1, VO = 4V Step (see Figure 2) G = +2,VO = 4V Step G = +2, VO = 0.5V Step G = +2, VO = 4VStep G = +2, f = 5MHz, VO = 2Vp-p RL = 100 RL 1k RL = 100 RL 1k f > 1MHz f > 1MHz f > 1MHz G = +2, NTSC, VO = 1.4Vp, RL = 150 G = +2, NTSC, VO = 1.4Vp, RL = 150 VO = 0V, RL = 1k VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V
UNITS MHz MHz MHz MHz MHz MHz dB MHz V/µs V/µs ns ns dBc dBc dBc dBc nV/Hz pA/Hz pA/Hz % deg k mV µV/°C µA nA/°C µA nA°/C V dB k || pF V mA mA µA ms ns dB pF mV mV V V µA V V mA mA dB °C °C/W °C/W
124
121
117
Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise-and-Fall Time Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Noninverting Input Current Noise Inverting Input Current Noise Differential Gain Differential Phase DC PERFORMANCE(4) Open-Loop Transimpedance Gain (ZOL) Input Offset Voltage Average Offset Voltage Drift Noninverting Input Bias Current Average Noninverting Input Bias Current Drift Inverting Input Bias Current Average Inverting Input Bias Current Drift INPUT Common-Mode Input Range(5) (CMIR) Common-Mode Rejection Ratio (CMRR) Noninverting Input Impedance Inverting Input Resistance (RI) OUTPUT Voltage Output Swing Current Output, Sourcing Current Output, Sinking Closed-Loop Output Impedance DISABLE (Disabled LOW) Power-Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn On Glitch Turn Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (DIS) POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Range Max Quiescent Current Min Quiescent Current Power-Supply Rejection Ratio (PSRR) TEMPERATURE RANGE Specification: D, DBV Thermal Resistance, JA D SO-8 DBV SOT-23-6
15 6.5 450 345
14 7.7 450 338
14 8.0 430 336
54 55 62 67 5.0 5.8 11.9
54 55 62 66 5.5 6.4 12.3
54 55 62 66 5.8 6.7 12.4
360 ±3.5 ±4.0 ±10
270 ±4.1 ±12 ±4.6 ±15 ±11 ±20 ±3.65 52
250 ±4.3 ±12 ±4.8 ± 15 ±11.5 ±20 ±3.60 52
VCM = 0V Open-Loop, DC 1k Load VO = 0 VO = 0 G = +2, f = 100kHz VDIS = 0 VIN = +1, See Figure 1 VIN = +1, See Figure 1 G = +2, 5MHz G = +2, RL = 150, VIN = 0 G = +2, RL = 150, VIN = 0
±3.75 60 50 2 4.5 ±4.1 150 110 0.007 100 60 40 70 1.7 ±70 ±20 3.4 1.8 80 ±5
±3.65 53
±4.0 130 100
±4.0 125 95
±3.9 120 90
150
170
180
VDIS = 0V
3.5 1.7 120
3.6 1.6 130
3.7 1.5 135
VS = ±5V VS = ±5V Input Referred
0.94 0.94 62 40 to +85
±6 1.03 0.85 55
±6 1.04 0.80 54
±6 1.05 0.77 54
Junction-to-Ambient 125 150
NOTES: (1) Junction temperature = ambient for 25°C tested specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +2°C at high temperature limit for over temperature tested specifications. (3) Test levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMR at ± CMIR limits.
OPA683
SBOS221B
3
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