LOW-VOLTAGE AND LOW-POWER STEREO AUDIO DIGITAL-TO-ANALOG CONVERTER WITH LINEOUT AMPLIFIER
FEATURES D Multilevel DAC Including Lineout Amplifier D Analog Performance = 2.4 V): D
Dynamic Range: 98 dB Typ THD+N at 0 dB: 0.007% Typ to 3.6-V Single Power Supply Low Power Dissipation: 2.4 V System Clock: 256fS, 384fS
Portable Audio Player Cellular Phone PDA Other Applications Requiring Low Voltage Operation
20-, 24-Bit Word Available Left-, Right-Justified and I2S Slave/Master Selectable Digital Attenuation: to 62 dB, 1 dB/Step 44.1-kHz Digital De-Emphasis Zero Cross Attenuation Digital Soft Mute Monaural Analog-In With Mixing Monaural Speaker Mode Hardware Control (PCM1773): Left-Justified and 44.1-kHz Digital De-Emphasis Monaural Analog-In With Mixing Pop-Noise-Free Circuit 3.3-V Tolerant
The PCM1772 and PCM1773 devices are CMOS, monolithic, integrated circuits which include stereo digital-to-analog converters, lineout circuitry, and support circuitry in small TSSOP-16 and VQFN-20 packages. The data converters utilize TI's enhanced multilevel - architecture, which employs noise shaping and multilevel amplitude quantization to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM1772 and PCM1773 devices accept several industry standard audio data formats with to 24-bit data, left-justified, I2S, etc., providing easy interfacing to audio DSP and decoder devices. Sampling rates to 50 kHz are supported. A full set of user-programmable functions are accessible through a 3-wire serial control port, which supports register write functions.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PRODUCT PACKGE PCM1772RGA PCM1773RGA PACKAGE TSSOP16 VQFN20 PACKAGE CODE to 85°C PACKAGE MARKING PCM1772 PCM1773 ORDERING NUMBER PCM1773RGA PCM1773RGAR TRANSPORT MEDIA Tube Tape and Reel Tube Tape and Reel Tray Tape and Reel Tray Tape and Reel
over operating free-air temperature range unless otherwise PCM1772 PCM1773 Supply voltage: VCC1, VCC2 Supply voltage differences: VCC1, VCC2 Ground voltage differences Digital input voltage Input current (any terminals except supplies) Operatingtemperature Storage temperature Junction temperature Lead temperature (soldering) 5 s
Package temperature (IR reflow, peak) s (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
all specifications = 44.1 kHz, system clock 256 fS and 24-bit data, 10 k, unless otherwise noted PARAMETER Resolution DATA FORMAT Audio data interface format Audio data bit length Audio data format Sampling frequency (fS) Internal system clock frequency DIGITAL INPUT/OUTPUT(1) Logic family VIH VIL IIH IIL VOH VOL Input logic level Input logic current Output logic level(2) VIN = VCC1 VIN 0 V IOH 2 mA IOL 0.7VCC1 0.3VCC1 CMOS compatible 10 10 Vdc µA Vdc (PCM1772) (PCM1773) Standard, I2S, left justified I2S, left justified 20-, 24-bit selectable MSB first, twos complement 384fS 50 kHz TEST CONDITIONS MIN TYP 24 MAX UNIT Bits
DYNAMIC PERFORMANCE LINE OUTPUT Full scale output voltage Dynamic range Signal-to-noise ratio THD+N Channel separation Load resistance dc ACCURACY Gain error Gain mismatch,channel-to-channel Bipolar zero error ANALOG LINE INPUT (MIXING CIRCUIT) Analog input voltage range Gain (analog input to line output) Analog input impedance THD+N DIGITAL FILTER PERFORMANCE Passband Stopband Passband ripple Stop band attenuation Group delay 44.1-kHz de-emphasis error (1) All logic inputs are 3.3-V tolerant and not terminated internally. (2) LRCK and BCK terminals dB 0.454fS AIN = 0.56VCC2 (peak-to-peak) k 0.584VCC2 VP-P VOUT 0.5VCC1 at BPZ %FSR 0 dB EIAJ, A-weighted EIAJ, A-weighted dB k VP-P dB