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Details, datasheet, quote on part number:PTH12010YAS
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PTHxx010Y --Series
15-A Non-Isolated DDR/QDR Memory Bus Termination Modules
SLTS223 MARCH 2004
Features
· VTT Bus T rmination Output e (Output Tracks the System VREF) · 15 A Output Current (12 A for 12-V Input) · 3.3-V, 5-V or 12-V Input Voltage · DDR & QDR Compatible · On/Off Inhibit (for VTT Standby) · Under-Voltage Lockout
NOMINAL SIZE = 1.37 in x 0.62 in (34,8 mm x 15,75 mm)
· · · ·
Operating Temp: 40 to +85 °C Efficiencies up to 91 % 62 W/in³ Power Density Output Over-Current Protection (Non-Latching, Auto-Reset) · Safety Agency Approvals (Pending): UL/cUL60950, EN60950, VDE · Point-of-Load Alliance (POLA) Compatible
Description
The PTHxx010Y are a series of readyto-use switching regulator modules from Te x a s Instruments designed specifically for bus termination in DDR and QDR m e m o r y applications. Operating from either a 3.3-V, 5-V or 12-V input, the modules generate a VTT output that will source or sink up to 15 A of current (12 A for 12-V input) to accurately track their V R E F input. V T T is the required bus termination supply voltage, and VREF is the reference voltage for the memory and chipset bus receiver comparators. VREF is usually set to half the VDDQ power supply voltage. The PTHxx010Y series employs an actively switched synchronous rectifier output to provide state-of-the-art stepdown switching conversion. The products are small in size (1.37 in × 0.62 in), and are an ideal choice where space, performance, and high efficiency are desired, along with the convenience of a ready-to-use module. Operating features include an on/off inhibit and output over-current protection (source mode only). The on/off inhibit feature allows the VTT bus to be turned off to save power in a standby mode of operation. To ensure tight load regulation, an output remote sense is also provided. Package options include both throughhole and surface mount configurations.
Pin Configuration
Pin
1 2 3 4 5 6 7 8 9 10
Function
GND Vin Inhibit * No Connect Vo Sense VTT GND VREF No Connect No Connect
* Denotes negative logic: Open = Normal operation Ground = VTT output on
Standard Application
VIN V DDQ
1k 1% 10 9 8
V REF VTT
1
7
1k 1% 2 3 CIN (Required)
PTHxx010Y (Top View)
6 4 5 V TT Termination Island
Con hf-Ceramic
Co1 Low-ESR (Required)
Co 2 Ceramic (Optional)
Standby GND
Q1 BSS138 (Optional)
SSTL-2 Data/ Address Bus
Ci n Co 1 Co 2 Co n
= = = =
Required capacitor; 470 µF (3.3-/5-V input), 560 µF (12-V input) Required low-ESR electrolyitic capacitor; 470 µF (3.3-/5-V input), 940 µF (12-V input). Ceramic capacitance for optimum response to a 3-A (±1.5-A) load transient. 200 µF (3.3-/5-V input), 400 µF (12-V input). Distributed hf-ceramic decoupling capacitors for V TT bus; as recommended for DDR memory appications.
For technical support and further information, visit http://power.ti.com
PTHxx010Y --Series
15-A Non-Isolated DDR/QDR Memory Bus Termination Modules
SLTS223 MARCH 2004
Ordering Information Input Voltage (PTHHH010Yxx)
Code 03 05 12 Input Voltage 3.3 V 5V 12 V
Package Options (PTHxx010YHH) (1)
Code AH AS Description Horiz. T/H SMD, Standard (3) Pkg Ref. (EUH) (EUJ)
(2)
Notes: (1) Add "T" to end of part number for tape and reel on SMD packages only. (2) Reference the applicable package reference drawing for the dimensions and PC board layout (3) "Standard" option specifies 63/37, Sn/Pb pin solder material.
Pin Descriptions
VIN: The positive input voltage power node to the module, which is referenced to common GND. GND: This is the common ground connection for the VIN and VTT power connections. It is also the 0-VDC reference for the control inputs. VREF: The module senses the voltage at this input to regulate the output voltage, VTT. The voltage at VREF is also the reference voltage for the system bus receiver comparators. It is normally set to precisely half the bus driver supply voltage (VDDQ ÷ 2), using a resistor divider (see standard application). The Thevenin impedance of the network driving the VREF pin should not exceed 500 . VTT: This is the regulated power output from the module with respect to the GND node, and is the tracking termination supply for the application data and address buses. It is precisely regulated to the voltage applied to the m o d u l e 's VREF input, and is active active about 20 ms after a valid input source is applied to the module. Once active it will track the voltage applied at VREF. Vo Sense: The sense input allows the regulation circuit to compensate for voltage drop between the module and the load. For optimal voltage accuracy Vo Sense should be connected to VTT. Inhibit: The Inhibit pin is an open-collector/drain negative logic input that is referenced to GND. Applying a lowlevel ground signal to this input turns off the output voltage, VTT. When the Inhibit is active, the input current drawn by the regulator is significantly reduced. If the Inhibit pin is left open circuit, the module will produce an output whenever a valid input source is applied.
Environmental & Absolute Maximum Ratings
Characteristics Control Input Voltage Operating T mperature Range e Solder Reflow T mperature e Storage T mperature e Mechanical Shock Mechanical Vibration Weight Flammability -- -- Symbols VREF Ta Treflow Ts
(Voltages are with respect to GND) Min 0.3 40 (i) 40 -- -- -- Typ -- -- -- 500 20 3.7 Max Vin + 0.3 85 235 (ii) 125 -- -- -- Units V °C °C °C G's G's grams
Conditions Over Vin Range Surface temperature of module body or pins -- Per Mil-STD-883D, Method 2002.3 1 msec, ½ Sine, mounted Mil-STD-883D, Method 2007.2 20-2000 Hz Meets UL 94V-O
Notes: (i) For operation below 0 °C the external capacitors m ust bave stable characteristics. use either a low ESR tantalum, Os-Con, or ceramic capacitor. (ii) During reflow of SMD package version do not elevate peak temperature of the module, pins or internal components above the stated maximum.
For technical support and further information, visit http://power.ti.com
PTHxx010Y --Series
15-A Non-Isolated DDR/QDR Memory Bus Termination Modules
SLTS223 MARCH 2004
Specifications
Characteristics Output Current
(Unless otherwise stated, T a =25 °C; nominal V in; VREF =1.25 V; C in, Co1, & Co 2 =typical values; and I o =Io max)
PTHxx010Y
Symbols Io Vin VREF VTT VREF Vr Io trip ttr Vtr UVLO Conditions Over VREF range, Over Io range PTH03010Y/PTH05010Y PTH12010Y PTH03010Y PTH05010Y PTH12010Y Min 0 0 2.95 4.5 10.8 0.55 10 -- -- -- -- -- -- -- -- -- -- -- 2.2 3.4 8.8 Vin 0.5 0.2 -- -- 300 200 470 (3) 560 (3) 0 -- 0 0 4 6 Typ -- -- -- -- -- -- -- 88 88 85 20 27.5 20 30 30 2.45 4.3 9.5 2.40 3.7 9 -- -- 130 10 350 250 -- -- 470 940 200 400 -- --
(4) (4) (4) (4)
Max ±15 (1) ±12 (1) 3.65 5.5 13.2 1.8 +10 -- -- -- -- -- -- -- 40 2.8 4.45 10.4 -- -- -- Open 0.6 -- -- 400 300 -- -- 8,200 6,600 300 600 -- --
(2)
Units A V V mV % mVpp A µSec mV V V V µA mA kHz µF
(5) (5)
Input Voltage Range Tracking Range for VREF Tracking T lerance to VREF o Efficiency Vo Ripple (pk-pk) Over-Current Threshold Load Transient Response Under-Voltage Lockout
Over line, load and temperature Io =10 A
PTH03010Y PTH05010Y PTH12010Y
Inhibit Control (pin3) Input High Voltage Input Low Voltage Input Low Current Input Standby Current Switching Frequency External Input Capacitance External Output Capacitance
VIH VIL IIL inhibit Iin inh s Cin Co1, Co2
20 MHz bandwidth Reset, PTH03010Y/PTH05010Y followed by auto-recovery PTH12010Y 15 A/µs load step, from 1.5 A to +1.5 A (See note 4) Recovery Time Vo over/undershoot Vin increasing PTH03010Y PTH05010Y PTH12010Y Vin decreasing PTH03010Y PTH05010Y PTH12010Y Referenced to GND Pin to GND Inhibit (pin 3) to GND Over Vin & Io ranges PTH03010Y/PTH05010Y PTH12010Y PTH03010Y/PTH05010Y PTH12010Y Capacitance value: non-ceramic PTH03010Y/PTH05010Y PTH12010Y ceramic PTH03010Y/PTH05010Y PTH12010Y Equiv. series resistance (non-ceramic) Per Bellcore TR-332 50 % stress, Ta =40 °C, ground benign
µF µF m 106 Hrs
(6)
Reliability
MTBF
Notes: (1) Rating is conditional on the module being soldered to a 4-layer PCB with 1 oz. copper. See the SOA curves or contact the factory for appropriate derating. (2) This control pin has an internal pull-up to the input voltage Vin. If it is left open-circuit the module will operate when input power is applied. A small low-leakage (<100 nA) MOSFET is recommended for control. For further information, consult the related application note. (3) An input capacitor is required for proper operation. The capacitor must be rated for a minimum of 800 mA rms of ripple current. (4) The typical value of external output capacitance value ensures that VTT meets the specified transient performance requirements for the memory bus terminations. Lower values of capacitance may be possible when the measured peak change in output current is consistently less than 3 A. (5) This is the calculated maximum. The minimum ESR limitation will often result in a lower value. Consult the application notes for further guidance. (6) This is the typcial ESR for all the electrolytic (non-ceramic) output capacitance. Use 7 m as the minimum when using max-ESR values to calculate.
For technical support and further information, visit http://power.ti.com
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