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Details, datasheet, quote on part number:SN100KT5578NT
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| Part: | SN100KT5578NT |
| Category: | Logic => Flip-Flops => D-Type Flip-Flops |
| Description: | ti SN100KT5578, Octal Ttl-to-ecl Translator With D-type Edge-triggered Flip-flops And Output Ena |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download SN100KT5578NT datasheet File size : 89 kB |
| Request For quote: | Find where to buy SN100KT5578NT
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Datasheet text preview:
SN100KT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE
SDZS13A APRIL 1990 REVISED OCTOBER 1990
· · · · · · ·
100K Compatible TTL Clock and ECL Control Inputs Noninverting Outputs Flow-Through Architecture Optimizes PCB Layout Center Pin VCC, VEE, and GND Configurations Minimize High-Speed Switching Noise Package Options Include "Small Outline" Packages and Standard Plastic DIPs ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015
DW OR NT PACKAGE (T0P VIEW)
1Q 2Q 3Q 4Q GND GND GND GND 5Q 6Q 7Q 8Q
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
1D 2D 3D 4D OE(ECL) VCC VEE CLK(TTL) 5D 6D 7D 8D
description
This octal TTL-to-ECL translator is designed to provide efficient translation between a TTL signal environment and a 100K ECL signal environment. This device is designed specifically to improve the performance and density of TTL-to-ECL CPU/ bus-oriented functions such as memoryaddress drivers,clock drivers, and bus-oriented receivers and transmitters. The eight flip-flops of the '5578 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic levels that were set up at the D inputs. The output-control input OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are off. The SN100KT5578 is characterized for operation from 0°C to 85°C. Function Table
INPUTS OE CLK D L L L H L X L H X X OUTPUT (ECL) Q L H Q0 L
logic symbol
CLK OE 17 20 TTL/ECL EN 1 2 3 4 4Q 9 10 11 12 5Q 6Q 7Q 8Q C1
1D 2D 3D 4D 5D 6D 7D 8D
24 23 22 21 16 15 14 13
1D
TTL/ECL
1Q 2Q 3Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1990, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SN100KT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE
SDZS13A APRIL 1990 REVISED OCTOBER 1990
logic diagram (positive logic)
OE CLK 20 17 TTL/ECL C1 1D 24 TTL/ECL 1D C1 2D 23 TTL/ECL 1D C1 1D C1 TTL/ECL 1D C1 TTL/ECL 1D C1 TTL/ECL 1D C1 TTL/ECL 1D C1 8D 13 TTL/ECL 1D 12 11 10 6Q 9 3 3Q 2 1 1Q
2Q
3D
22
TTL/ECL
4
4D
21
4Q
5D
16
5Q
6D
15
7D
14
7Q
8Q
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN100KT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE
SDZS13A APRIL 1990 REVISED OCTOBER 1990
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Supply voltage range, VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V to 0 V Input voltage range (TTL) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 V to 7 V Input voltage range (ECL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE to 0 V Input current range (TTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA to 5 mA Current out of any output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Operating ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The TTL input voltage ratings may be exceeded provided the input current ratings are observed.
recommended operating conditions
MIN VCC VEE VIH VIL IIK VIH VIL TA TTL supply voltage ECL supply voltage TTL high-level input voltage TTL low-level input voltage TTL input clamp current ECL high-level input voltage ECL low-level input voltage Operating ambient temperature (see Note 2) 1165 1810 0 4.5 4.2 2 0.8 18 880 1475 85 NOM 5 4.5 MAX 5.5 4.8 UNIT V V V V mA mV mV °C
electrical characteristics over recommended operating ambient temperature range (unless otherwise noted) (see Note 2)
PARAMETER VIK II IIH IIL IIH IIL VOH VOL ICCH ICCL D inputs and CLK D inputs and CLK D inputs and CLK D inputs and CLK OE only OE only VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, TEST CONDITIONS VEE = 4.2 V, VEE = 4.8 V, VEE = 4.8 V, VEE = 4.8 V, VEE = 4.8 V, VEE = 4.8 V, VEE = 4.5 V ± 0.3 V, VEE = 4.5 V ± 0.3 V, VEE = 4.8 V VEE = 4.8 V II = 18 mA VI = 7 V VI = 2.7 V VI = 0.5 V VIH = 880 mV VIL = 1810 mV See Note 3 See Note 3 0.50 1020 1810 17 14.5 880 1620 24 21 MIN TYP§ MAX 1.2 0.1 20 0.5 350 UNIT V mA µA mA µA µA mV mV mA mA
IEE VCC = 5.5 V, VEE = 4.8 V 104 149 mA Ci VCC = 5 V, VEE = 4.5 V, f = 10 MHz 4 pF The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic levels only. § All typical values are at VCC = 5 V, VEE = 4.5 V, TA = 25°C. NOTES: 2. Each 100KT series circuit has been designed to meet the dc specifications shown in the test table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear ft/min is maintained. 3. Outputs are terminated through a 50- resistor to 2 V.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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