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Details, datasheet, quote on part number:SN54ABT16863WD
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Datasheet text preview:
SN54ABT16863, SN74ABT16863 18-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS225C JUNE 1992 REVISED MAY 1997
D D D D D D D D D
Members of the Texas Instruments Widebus TM Family State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up and Power Down Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout High-Drive Outputs (32-mA IOH, 64-mA IOL) Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
SN54ABT16863 . . . WD PACKAGE SN74ABT16863 . . . DL PACKAGE (TOP VIEW)
description
The 'ABT16863 are 18-bit noninverting transceivers designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements. The 'ABT16863 can be used as two 9-bit transceivers or one 18-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the output-enable (OEAB or OEBA) inputs.
1OEAB 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 1B7 GND 1B8 1B9 GND GND 2B1 2B2 GND 2B3 2B4 2B5 VCC 2B6 2B7 GND 2B8 2B9 2OEAB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OEBA 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 1A7 GND 1A8 1A9 GND GND 2A1 2A2 GND 2A3 2A4 2A5 VCC 2A6 2A7 GND 2A8 2A9 2OEBA
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16863 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT16863 is characterized for operation from 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-B are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 1997, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
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SN54ABT16863, SN74ABT16863 18-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS225C JUNE 1992 REVISED MAY 1997
FUNCTION TABLE (each 9-bit section) INPUTS OPERATION OEAB H L H OEBA L H H B data to A bus A data to B bus Isolation
logic symbol
56 1OEBA 1OEAB 2OEBA 2OEAB 1A1 28 55 1 29 EN1 EN2 EN3 EN4 1 1 1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 2A1 54 52 51 49 48 47 45 44 41 3 1 1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 40 38 37 36 34 33 31 30 4 17 19 20 21 23 24 26 27 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 2 3 5 6 8 9 10 12 13 16 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 2B1 2 1B1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT16863, SN74ABT16863 18-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS225C JUNE 1992 REVISED MAY 1997
logic diagram (positive logic)
1OEBA 1OEAB 56 1 2OEAB 2OEBA 29 28
55 1A1
2 1B1 2A1
41
16 2B1
To Eight Other Channels
To Eight Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT16863 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT16863 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABT16863 MIN VCC VIH VIL VI IOH IOL t/v t/VCC Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Power-up ramp rate Outputs enabled 200 55 125 0 4.5 2 0.8 VCC 24 48 10 200 40 85 0 MAX 5.5 SN74ABT16863 MIN 4.5 2 0.8 VCC 32 64 10 MAX 5.5 UNIT V V V V mA mA ns/V µs/V °C
TA Operating free-air temperature NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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